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packet.h File Reference

Command packet opcodes, events and builders. More...

#include <rex/assert.h>
#include <rex/memory/endian.h>
#include <rex/types.h>

Go to the source code of this file.

Namespaces

namespace  rex

Enumerations

enum  rex::xenos::Event : u8 {
  VS_DEALLOC = 0 , PS_DEALLOC = 1 , VS_DONE_TS = 2 , PS_DONE_TS = 3 ,
  CACHE_FLUSH_TS = 4 , CONTEXT_DONE = 5 , CACHE_FLUSH = 6 , VIZQUERY_START = 7 ,
  VIZQUERY_END = 8 , SC_WAIT_WC = 9 , MPASS_PS_CP_REFETCH = 10 , MPASS_PS_RST_START = 11 ,
  MPASS_PS_INCR_START = 12 , RST_PIX_CNT = 13 , RST_VTX_CNT = 14 , TILE_FLUSH = 15 ,
  CACHE_FLUSH_AND_INV_TS_EVENT = 20 , ZPASS_DONE = 21 , CACHE_FLUSH_AND_INV_EVENT = 22 , PERFCOUNTER_START = 23 ,
  PERFCOUNTER_STOP = 24 , SCREEN_EXT_INIT = 25 , SCREEN_EXT_RPT = 26 , VS_FETCH_DONE_TS = 27
}
enum  rex::xenos::Type3Opcode : u8 {
  rex::xenos::PM4_ME_INIT = 0x48 , rex::xenos::PM4_NOP = 0x10 , rex::xenos::PM4_INDIRECT_BUFFER = 0x3f , rex::xenos::PM4_INDIRECT_BUFFER_PFD = 0x37 ,
  PM4_WAIT_FOR_IDLE = 0x26 , rex::xenos::PM4_WAIT_REG_MEM = 0x3c , PM4_WAIT_REG_EQ = 0x52 , PM4_WAIT_REG_GTE = 0x53 ,
  PM4_WAIT_UNTIL_READ = 0x5c , rex::xenos::PM4_WAIT_IB_PFD_COMPLETE = 0x5d , rex::xenos::PM4_REG_RMW = 0x21 , rex::xenos::PM4_REG_TO_MEM = 0x3e ,
  rex::xenos::PM4_MEM_WRITE = 0x3d , rex::xenos::PM4_MEM_WRITE_CNTR = 0x4f , rex::xenos::PM4_COND_EXEC = 0x44 , rex::xenos::PM4_COND_WRITE = 0x45 ,
  rex::xenos::PM4_EVENT_WRITE = 0x46 , rex::xenos::PM4_EVENT_WRITE_SHD = 0x58 , rex::xenos::PM4_EVENT_WRITE_CFL = 0x59 , rex::xenos::PM4_EVENT_WRITE_EXT = 0x5a ,
  rex::xenos::PM4_EVENT_WRITE_ZPD = 0x5b , rex::xenos::PM4_DRAW_INDX = 0x22 , rex::xenos::PM4_DRAW_INDX_2 = 0x36 , rex::xenos::PM4_DRAW_INDX_BIN = 0x34 ,
  rex::xenos::PM4_DRAW_INDX_2_BIN = 0x35 , rex::xenos::PM4_VIZ_QUERY = 0x23 , rex::xenos::PM4_SET_STATE = 0x25 , rex::xenos::PM4_SET_CONSTANT = 0x2d ,
  rex::xenos::PM4_SET_CONSTANT2 = 0x55 , rex::xenos::PM4_SET_SHADER_CONSTANTS = 0x56 , rex::xenos::PM4_LOAD_ALU_CONSTANT = 0x2f , rex::xenos::PM4_IM_LOAD = 0x27 ,
  rex::xenos::PM4_IM_LOAD_IMMEDIATE = 0x2b , rex::xenos::PM4_LOAD_CONSTANT_CONTEXT = 0x2e , rex::xenos::PM4_INVALIDATE_STATE = 0x3b , rex::xenos::PM4_SET_SHADER_BASES = 0x4A ,
  rex::xenos::PM4_SET_BIN_BASE_OFFSET = 0x4B , rex::xenos::PM4_SET_BIN_MASK = 0x50 , rex::xenos::PM4_SET_BIN_SELECT = 0x51 , rex::xenos::PM4_CONTEXT_UPDATE = 0x5e ,
  PM4_INTERRUPT = 0x54 , rex::xenos::PM4_XE_SWAP = 0x64 , rex::xenos::PM4_IM_STORE = 0x2c , rex::xenos::PM4_SET_BIN_MASK_LO = 0x60 ,
  PM4_SET_BIN_MASK_HI = 0x61 , PM4_SET_BIN_SELECT_LO = 0x62 , PM4_SET_BIN_SELECT_HI = 0x63
}

Functions

u32 rex::xenos::BuildPacketType0 (u16 index, u16 count, bool one_reg=false)
u32 rex::xenos::BuildPacketType1 (u16 index_1, u16 index_2)
constexpr u32 rex::xenos::BuildPacketType2 ()
u32 rex::xenos::BuildPacketType3 (Type3Opcode opcode, u16 count, bool predicate=false)

Variables

constexpr memory::FourCCT rex::xenos::kSwapSignature = memory::make_fourcc("SWAP")

Detailed Description

Command packet opcodes, events and builders.

Copyright
Copyright (c) 2026 Tom Clay tomc@.nosp@m.tcte.nosp@m.chstu.nosp@m.ff.c.nosp@m.om All rights reserved.
License
BSD 3-Clause License See LICENSE file in the project root for full license text.
Remarks
Derived from Xenia's xenia/gpu/xenos.h (Ben Vanik, 2020).

Enumeration Type Documentation

◆ Event

enum rex::xenos::Event : u8

Event values for VGT_EVENT_INITIATOR.

◆ Type3Opcode

enum rex::xenos::Type3Opcode : u8

Type 3 packet opcodes (IT_OPCODE) in the ring buffer.

Enumerator
PM4_ME_INIT 

Initialize the CP micro engine.

PM4_NOP 

Skip N 32 bit words.

PM4_INDIRECT_BUFFER 

Indirect buffer dispatch, prefetched.

PM4_INDIRECT_BUFFER_PFD 

Indirect buffer dispatch, pipelined init.

PM4_WAIT_REG_MEM 

Wait for a register or memory value.

PM4_WAIT_IB_PFD_COMPLETE 

Wait for IB_PFD base and size writes.

PM4_REG_RMW 

Register read, modify and write.

PM4_REG_TO_MEM 

Copy a register to memory.

PM4_MEM_WRITE 

Write N 32 bit words to memory.

PM4_MEM_WRITE_CNTR 

Write CP_PROG_COUNTER to memory.

PM4_COND_EXEC 

Conditionally execute packets.

PM4_COND_WRITE 

Conditionally write memory or a register.

PM4_EVENT_WRITE 

Event that writes memory on completion.

PM4_EVENT_WRITE_SHD 

Vertex or pixel shader done event.

PM4_EVENT_WRITE_CFL 

Cache flush done event.

PM4_EVENT_WRITE_EXT 

Screen extent event.

PM4_EVENT_WRITE_ZPD 

Z pass done event.

PM4_DRAW_INDX 

Fetch the index buffer and draw.

PM4_DRAW_INDX_2 

Draw with indices in the packet.

PM4_DRAW_INDX_BIN 

Fetch the index buffer and bin IDs and draw.

PM4_DRAW_INDX_2_BIN 

Fetch bin IDs and draw with packet indices.

PM4_VIZ_QUERY 

Visibility query begin or end.

PM4_SET_STATE 

Fetch state and start shader code DMA.

PM4_SET_CONSTANT 

Load a constant into the chip and memory.

PM4_SET_CONSTANT2 

Incremental state update.

PM4_SET_SHADER_CONSTANTS 

Incremental constant update.

PM4_LOAD_ALU_CONSTANT 

Load constants from memory.

PM4_IM_LOAD 

Load instruction memory from a pointer.

PM4_IM_LOAD_IMMEDIATE 

Load instruction memory from the packet.

PM4_LOAD_CONSTANT_CONTEXT 

Load constants from a memory location.

PM4_INVALIDATE_STATE 

Invalidate selected state pointers.

PM4_SET_SHADER_BASES 

Change the instruction memory partition.

PM4_SET_BIN_BASE_OFFSET 

Offset added to BIN_BASE of binned draws.

PM4_SET_BIN_MASK 

Set the 64 bit BIN_MASK.

PM4_SET_BIN_SELECT 

Set the 64 bit BIN_SELECT.

PM4_CONTEXT_UPDATE 

Update the current context if needed.

PM4_XE_SWAP 

Opcode that VdSwap writes to present.

PM4_IM_STORE 

Copy instruction memory to system memory.

PM4_SET_BIN_MASK_LO 

Set the low BIN_MASK dword for tiled rendering.

Function Documentation

◆ BuildPacketType0()

u32 rex::xenos::BuildPacketType0 ( u16 index,
u16 count,
bool one_reg = false )
inline

Builds a type 0 packet header that writes consecutive registers.

Layout is ttcccccc cccccccc oiiiiiii iiiiiiii.

Parameters
indexFirst register index, up to 0x7FFF.
countRegister count, 1 to 0x4000.
one_regTrue to write every value to the register at index.

◆ BuildPacketType1()

u32 rex::xenos::BuildPacketType1 ( u16 index_1,
u16 index_2 )
inline

Builds a type 1 packet header that writes two registers.

Layout tt?????? ??222222 22222111 11111111.

Parameters
index_1First register index, up to 0x7FF.
index_2Second register index, up to 0x7FF.

◆ BuildPacketType2()

u32 rex::xenos::BuildPacketType2 ( )
constexpr

Builds a type 2 packet, a single dword no op.

◆ BuildPacketType3()

u32 rex::xenos::BuildPacketType3 ( Type3Opcode opcode,
u16 count,
bool predicate = false )
inline

Builds a type 3 packet header.

Layout is ttcccccc cccccccc ?ooooooo ???????p.

Parameters
countPayload dword count, 1 to 0x4000.
predicateWhether the packet is predicated.

Variable Documentation

◆ kSwapSignature

memory::FourCCT rex::xenos::kSwapSignature = memory::make_fourcc("SWAP")
constexpr

Signature that VdSwap writes as the first payload dword of its swap packet.