ucode.h

 
#pragma once
 
#include <cstdint>
 
#include <rex/types.h>
#include <rex/assert.h>
#include <rex/xenos/fetch.h>
#include <rex/xenos/format.h>
#include <rex/xenos/state.h>
#include <rex/math.h>
#include <rex/platform.h>
 
/*
 * Parts of this code come from the freedreno project:
 * https://github.com/freedreno/freedreno/blob/master/includes/instr-a2xx.h
 *
 * Copyright (c) 2012 Rob Clark <robdclark@gmail.com>
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 * SOFTWARE.
 */

namespace rex::xenos::ucode {
 
// NOLINTNEXTLINE(performance-enum-size): Xenos bit field, MSVC packs per type
enum class ControlFlowOpcode : u32 {
  kNop = 0,
  kExec = 1,
  kExecEnd = 2,
  kCondExec = 3,
  kCondExecEnd = 4,
  kCondExecPred = 5,
  kCondExecPredEnd = 6,
  kLoopStart = 7,
  kLoopEnd = 8,
  kCondCall = 9,
  kReturn = 10,
  kCondJmp = 11,
  kAlloc = 12,
  kCondExecPredClean = 13,
  kCondExecPredCleanEnd = 14,
  kMarkVSFetchDone = 15,
};

constexpr bool IsControlFlowOpcodeExec(ControlFlowOpcode opcode) {
  return opcode == ControlFlowOpcode::kExec || opcode == ControlFlowOpcode::kExecEnd ||
         opcode == ControlFlowOpcode::kCondExec || opcode == ControlFlowOpcode::kCondExecEnd ||
         opcode == ControlFlowOpcode::kCondExecPred ||
         opcode == ControlFlowOpcode::kCondExecPredEnd ||
         opcode == ControlFlowOpcode::kCondExecPredClean ||
         opcode == ControlFlowOpcode::kCondExecPredCleanEnd;
}

constexpr bool IsControlFlowOpcodeEnd(ControlFlowOpcode opcode) {
  return opcode == ControlFlowOpcode::kExecEnd || opcode == ControlFlowOpcode::kCondExecEnd ||
         opcode == ControlFlowOpcode::kCondExecPredEnd ||
         opcode == ControlFlowOpcode::kCondExecPredCleanEnd;
}

constexpr bool HasControlFlowCondExecCleanPredicate(ControlFlowOpcode opcode) {
  return opcode == ControlFlowOpcode::kCondExecPredClean ||
         opcode == ControlFlowOpcode::kCondExecPredCleanEnd;
}

// NOLINTNEXTLINE(performance-enum-size): Xenos bit field, MSVC packs per type
enum class AddressingMode : u32 {
  kRelative = 0,
  kAbsolute = 1,
};
 
// NOLINTNEXTLINE(performance-enum-size): Xenos bit field, MSVC packs per type
enum class AllocType : u32 {
  kNone = 0,
  kVsPosition = 1,
  kVsInterpolators = 2,
  kPsColors = 2,
  kMemory = 3,
};

struct ControlFlowExecInstruction {
  ControlFlowOpcode GetOpcode() const { return opcode_; }
  AddressingMode GetAddressingMode() const { return address_mode_; }
  u32 GetAddress() const { return address_; }
  u32 GetCount() const { return count_; }
  u32 GetSequence() const { return sequence_; }
  bool IsPredicateClean() const { return is_predicate_clean_ == 1; }
  bool IsYield() const { return is_yield_ == 1; }
 
 private:
  u32 address_ : 12;
  u32 count_ : 3;
  u32 is_yield_ : 1;
  u32 sequence_ : 12;
  [[maybe_unused]] u32 vc_hi_ : 4;
 
  [[maybe_unused]] u32 vc_lo_ : 2;
  u32 : 7;
  u32 is_predicate_clean_ : 1;
  u32 : 1;
  AddressingMode address_mode_ : 1;
  ControlFlowOpcode opcode_ : 4;
};
REX_STATIC_ASSERT_SIZE(ControlFlowExecInstruction, sizeof(u32) * 2);

struct ControlFlowCondExecInstruction {
  ControlFlowOpcode GetOpcode() const { return opcode_; }
  AddressingMode GetAddressingMode() const { return address_mode_; }
  u32 GetAddress() const { return address_; }
  u32 GetCount() const { return count_; }
  u32 GetSequence() const { return sequence_; }
  u32 GetBoolAddress() const { return bool_address_; }
  bool GetCondition() const { return condition_ == 1; }
  bool IsYield() const { return is_yield_ == 1; }
 
 private:
  u32 address_ : 12;
  u32 count_ : 3;
  u32 is_yield_ : 1;
  u32 sequence_ : 12;
  [[maybe_unused]] u32 vc_hi_ : 4;
 
  [[maybe_unused]] u32 vc_lo_ : 2;
  u32 bool_address_ : 8;
  u32 condition_ : 1;
  AddressingMode address_mode_ : 1;
  ControlFlowOpcode opcode_ : 4;
};
REX_STATIC_ASSERT_SIZE(ControlFlowCondExecInstruction, sizeof(u32) * 2);

struct ControlFlowCondExecPredInstruction {
  ControlFlowOpcode GetOpcode() const { return opcode_; }
  AddressingMode GetAddressingMode() const { return address_mode_; }
  u32 GetAddress() const { return address_; }
  u32 GetCount() const { return count_; }
  u32 GetSequence() const { return sequence_; }
  bool IsPredicateClean() const { return is_predicate_clean_ == 1; }
  bool GetCondition() const { return condition_ == 1; }
  bool IsYield() const { return is_yield_ == 1; }
 
 private:
  u32 address_ : 12;
  u32 count_ : 3;
  u32 is_yield_ : 1;
  u32 sequence_ : 12;
  [[maybe_unused]] u32 vc_hi_ : 4;
 
  [[maybe_unused]] u32 vc_lo_ : 2;
  u32 : 7;
  u32 is_predicate_clean_ : 1;
  u32 condition_ : 1;
  AddressingMode address_mode_ : 1;
  ControlFlowOpcode opcode_ : 4;
};
REX_STATIC_ASSERT_SIZE(ControlFlowCondExecPredInstruction, sizeof(u32) * 2);

struct ControlFlowLoopStartInstruction {
  ControlFlowOpcode GetOpcode() const { return opcode_; }
  AddressingMode GetAddressingMode() const { return address_mode_; }
  u32 GetAddress() const { return address_; }
  bool IsRepeat() const { return is_repeat_; }
  u32 GetLoopID() const { return loop_id_; }
 
 private:
  u32 address_ : 13;
  u32 is_repeat_ : 1;
  u32 : 2;
  u32 loop_id_ : 5;
  u32 : 11;
 
  u32 : 11;
  AddressingMode address_mode_ : 1;
  ControlFlowOpcode opcode_ : 4;
};
REX_STATIC_ASSERT_SIZE(ControlFlowLoopStartInstruction, sizeof(u32) * 2);

struct ControlFlowLoopEndInstruction {
  ControlFlowOpcode GetOpcode() const { return opcode_; }
  AddressingMode GetAddressingMode() const { return address_mode_; }
  u32 GetAddress() const { return address_; }
  u32 GetLoopID() const { return loop_id_; }
  bool IsPredicatedBreak() const { return is_predicated_break_; }
  bool GetCondition() const { return condition_ == 1; }
 
 private:
  u32 address_ : 13;
  u32 : 3;
  u32 loop_id_ : 5;
  u32 is_predicated_break_ : 1;
  u32 : 10;
 
  u32 : 10;
  u32 condition_ : 1;
  AddressingMode address_mode_ : 1;
  ControlFlowOpcode opcode_ : 4;
};
REX_STATIC_ASSERT_SIZE(ControlFlowLoopEndInstruction, sizeof(u32) * 2);

struct ControlFlowCondCallInstruction {
  ControlFlowOpcode GetOpcode() const { return opcode_; }
  AddressingMode GetAddressingMode() const { return address_mode_; }
  u32 GetAddress() const { return address_; }
  bool IsUnconditional() const { return is_unconditional_; }
  bool IsPredicated() const { return is_predicated_; }
  u32 GetBoolAddress() const { return bool_address_; }
  bool GetCondition() const { return condition_ == 1; }
 
 private:
  u32 address_ : 13;
  u32 is_unconditional_ : 1;
  u32 is_predicated_ : 1;
  u32 : 17;
 
  u32 : 2;
  u32 bool_address_ : 8;
  u32 condition_ : 1;
  AddressingMode address_mode_ : 1;
  ControlFlowOpcode opcode_ : 4;
};
REX_STATIC_ASSERT_SIZE(ControlFlowCondCallInstruction, sizeof(u32) * 2);

struct ControlFlowReturnInstruction {
  ControlFlowOpcode GetOpcode() const { return opcode_; }
  AddressingMode GetAddressingMode() const { return address_mode_; }
 
 private:
  u32 : 32;
 
  u32 : 11;
  AddressingMode address_mode_ : 1;
  ControlFlowOpcode opcode_ : 4;
};
REX_STATIC_ASSERT_SIZE(ControlFlowReturnInstruction, sizeof(u32) * 2);

struct ControlFlowCondJmpInstruction {
  ControlFlowOpcode GetOpcode() const { return opcode_; }
  AddressingMode GetAddressingMode() const { return address_mode_; }
  u32 GetAddress() const { return address_; }
  bool IsUnconditional() const { return is_unconditional_; }
  bool IsPredicated() const { return is_predicated_; }
  u32 GetBoolAddress() const { return bool_address_; }
  bool GetCondition() const { return condition_ == 1; }
 
 private:
  u32 address_ : 13;
  u32 is_unconditional_ : 1;
  u32 is_predicated_ : 1;
  u32 : 17;
 
  u32 : 1;
  [[maybe_unused]] u32 direction_ : 1;
  u32 bool_address_ : 8;
  u32 condition_ : 1;
  AddressingMode address_mode_ : 1;
  ControlFlowOpcode opcode_ : 4;
};
REX_STATIC_ASSERT_SIZE(ControlFlowCondJmpInstruction, sizeof(u32) * 2);

struct ControlFlowAllocInstruction {
  ControlFlowOpcode GetOpcode() const { return opcode_; }
  u32 GetSize() const { return size_; }
  AllocType GetAllocType() const { return alloc_type_; }
 
 private:
  u32 size_ : 3;
  u32 : 29;
 
  u32 : 8;
  u32 : 1;
  AllocType alloc_type_ : 2;
  u32 : 1;
  ControlFlowOpcode opcode_ : 4;
};
REX_STATIC_ASSERT_SIZE(ControlFlowAllocInstruction, sizeof(u32) * 2);

union ControlFlowInstruction {
  ControlFlowOpcode GetOpcode() const { return opcode_value; }
 
  ControlFlowExecInstruction exec;                   
  ControlFlowCondExecInstruction cond_exec;          
  ControlFlowCondExecPredInstruction cond_exec_pred; 
  ControlFlowLoopStartInstruction loop_start;        
  ControlFlowLoopEndInstruction loop_end;            
  ControlFlowCondCallInstruction cond_call;          
  ControlFlowReturnInstruction ret;                  
  ControlFlowCondJmpInstruction cond_jmp;            
  ControlFlowAllocInstruction alloc;                 
 
  struct {
    u32 dword_0;
    u32 dword_1;
  };
  struct {
    u32 unused_0 : 32;
    u32 unused_1 : 12;
    ControlFlowOpcode opcode_value : 4;
  };
};
REX_STATIC_ASSERT_SIZE(ControlFlowInstruction, sizeof(u32) * 2);

inline void UnpackControlFlowInstructions(const u32* dwords, ControlFlowInstruction* out_ab) {
  u32 dword_0 = dwords[0];
  u32 dword_1 = dwords[1];
  u32 dword_2 = dwords[2];
  out_ab[0].dword_0 = dword_0;
  out_ab[0].dword_1 = dword_1 & 0xFFFF;
  out_ab[1].dword_0 = (dword_1 >> 16) | (dword_2 << 16);
  out_ab[1].dword_1 = dword_2 >> 16;
}
 
// NOLINTNEXTLINE(performance-enum-size): Xenos bit field, MSVC packs per type
enum class FetchOpcode : u32 {
  kVertexFetch = 0,

  kTextureFetch = 1,

  kGetTextureBorderColorFrac = 16,

  kGetTextureComputedLOD = 17,

  kGetTextureGradients = 18,

  kGetTextureWeights = 19,

  kSetTextureLOD = 24,
  kSetTextureGradientsHorz = 25,
  kSetTextureGradientsVert = 26,
};

enum class FetchDestinationSwizzle : u8 {
  kX = 0,
  kY = 1,
  kZ = 2,
  kW = 3,
  k0 = 4,
  k1 = 5,
  kKeep = 7,
};

constexpr FetchDestinationSwizzle GetFetchDestinationComponentSwizzle(u32 swizzle, u32 component) {
  return static_cast<FetchDestinationSwizzle>((swizzle >> (3 * component)) & 0b111);
}

struct alignas(u32) VertexFetchInstruction {
  FetchOpcode GetOpcode() const { return data_.opcode_value; }
 
  bool IsPredicated() const { return data_.is_predicated; }
  bool GetPredicateCondition() const { return data_.pred_condition == 1; }
  u32 GetFetchConstantIndex() const { return data_.const_index * 3 + data_.const_index_sel; }
 
  u32 GetDest() const { return data_.dst_reg; }
  u32 GetDestSwizzle() const { return data_.dst_swiz; }
  bool IsDestRelative() const { return data_.dst_reg_am; }
  u32 GetSrcReg() const { return data_.src_reg; }
  u32 GetSrcSwizzle() const { return data_.src_swiz; }
  bool IsSrcRelative() const { return data_.src_reg_am; }

  u32 GetPrefetchCount() const { return data_.prefetch_count; }
  bool IsMiniFetch() const { return data_.is_mini_fetch == 1; }
 
  xenos::VertexFormat GetDataFormat() const { return data_.format; }
  int GetExpAdjust() const { return data_.exp_adjust; }
  bool IsSigned() const { return data_.format_comp_all == 1; }
  bool IsNormalized() const { return data_.num_format_all == 0; }
  xenos::SignedRepeatingFractionMode GetSignedRFMode() const { return data_.signed_rf_mode_all; }
  bool IsIndexRounded() const { return data_.is_index_rounded == 1; }
  u32 GetStride() const { return data_.stride; }
  i32 GetOffset() const { return data_.offset; }
 
 private:
  struct Data {
    struct {
      FetchOpcode opcode_value : 5;
      u32 src_reg : 6;
      u32 src_reg_am : 1;
      u32 dst_reg : 6;
      u32 dst_reg_am : 1;
      u32 must_be_one : 1;
      u32 const_index : 5;     
      u32 const_index_sel : 2; 
      u32 prefetch_count : 3;  
      u32 src_swiz : 2;        
    };
    struct {
      u32 dst_swiz : 12;
      u32 format_comp_all : 1; 
      u32 num_format_all : 1;  
      xenos::SignedRepeatingFractionMode signed_rf_mode_all : 1;
      u32 is_index_rounded : 1;
      xenos::VertexFormat format : 6;
      u32 reserved2 : 2;
      i32 exp_adjust : 6;
      u32 is_mini_fetch : 1; 
      u32 is_predicated : 1;
    };
    struct {
      u32 stride : 8;  
      i32 offset : 23; 
      u32 pred_condition : 1;
    };
  };
  Data data_;
};
REX_STATIC_ASSERT_SIZE(VertexFetchInstruction, sizeof(u32) * 3);

struct alignas(u32) TextureFetchInstruction {
  FetchOpcode GetOpcode() const { return data_.opcode_value; }
 
  bool IsPredicated() const { return data_.is_predicated; }
  bool GetPredicateCondition() const { return data_.pred_condition == 1; }
  u32 GetFetchConstantIndex() const { return data_.const_index; }
 
  u32 GetDest() const { return data_.dst_reg; }
  u32 GetDestSwizzle() const { return data_.dst_swiz; }
  bool IsDestRelative() const { return data_.dst_reg_am; }
  u32 GetSrcReg() const { return data_.src_reg; }
  u32 GetSrcSwizzle() const { return data_.src_swiz; }
  bool IsSrcRelative() const { return data_.src_reg_am; }
 
  xenos::FetchOpDimension GetDimension() const { return data_.dimension; }
  bool IsFetchValidOnly() const { return data_.fetch_valid_only == 1; }
  bool HasUnnormalizedCoordinates() const { return data_.tx_coord_denorm == 1; }
  bool HasMagFilter() const { return data_.mag_filter != xenos::TextureFilter::kUseFetchConst; }
  xenos::TextureFilter GetMagFilter() const { return data_.mag_filter; }
  bool HasMinFilter() const { return data_.min_filter != xenos::TextureFilter::kUseFetchConst; }
  xenos::TextureFilter GetMinFilter() const { return data_.min_filter; }
  bool HasMipFilter() const { return data_.mip_filter != xenos::TextureFilter::kUseFetchConst; }
  xenos::TextureFilter GetMipFilter() const { return data_.mip_filter; }
  bool HasAnisoFilter() const { return data_.aniso_filter != xenos::AnisoFilter::kUseFetchConst; }
  xenos::AnisoFilter GetAnisoFilter() const { return data_.aniso_filter; }
  bool HasVolMagFilter() const {
    return data_.vol_mag_filter != xenos::TextureFilter::kUseFetchConst;
  }
  xenos::TextureFilter GetVolMagFilter() const { return data_.vol_mag_filter; }
  bool HasVolMinFilter() const {
    return data_.vol_min_filter != xenos::TextureFilter::kUseFetchConst;
  }
  xenos::TextureFilter GetVolMinFilter() const { return data_.vol_min_filter; }
  bool IsComputedLODUsed() const { return data_.use_comp_lod == 1; }
  bool IsRegisterLODUsed() const { return data_.use_reg_lod == 1; }
  bool HasRegisterGradients() const { return data_.use_reg_gradients == 1; }
  xenos::SampleLocation GetSampleLocation() const { return data_.sample_location; }
  f32 GetLODBias() const { return static_cast<f32>(data_.lod_bias) * (1.0f / 16.0f); }
  f32 GetOffsetX() const { return static_cast<f32>(data_.offset_x) * 0.5f; }
  f32 GetOffsetY() const { return static_cast<f32>(data_.offset_y) * 0.5f; }
  f32 GetOffsetZ() const { return static_cast<f32>(data_.offset_z) * 0.5f; }
 
 private:
  struct Data {
    struct {
      FetchOpcode opcode_value : 5;
      u32 src_reg : 6;
      u32 src_reg_am : 1;
      u32 dst_reg : 6;
      u32 dst_reg_am : 1;
      u32 fetch_valid_only : 1;
      u32 const_index : 5;
      u32 tx_coord_denorm : 1;
      u32 src_swiz : 6; 
    };
    struct {
      u32 dst_swiz : 12;
      xenos::TextureFilter mag_filter : 2;
      xenos::TextureFilter min_filter : 2;
      xenos::TextureFilter mip_filter : 2;
      xenos::AnisoFilter aniso_filter : 3;
      xenos::ArbitraryFilter arbitrary_filter : 3;
      xenos::TextureFilter vol_mag_filter : 2;
      xenos::TextureFilter vol_min_filter : 2;
      u32 use_comp_lod : 1;
      u32 use_reg_lod : 1;
      u32 unknown : 1;
      u32 is_predicated : 1;
    };
    struct {
      u32 use_reg_gradients : 1;
      xenos::SampleLocation sample_location : 1;
      i32 lod_bias : 7; 
      u32 unused : 5;
      xenos::FetchOpDimension dimension : 2;
      i32 offset_x : 5; 
      i32 offset_y : 5;
      i32 offset_z : 5;
      u32 pred_condition : 1;
    };
  };
  Data data_;
};
REX_STATIC_ASSERT_SIZE(TextureFetchInstruction, sizeof(u32) * 3);

union alignas(u32) FetchInstruction {
 public:
  FetchOpcode GetOpcode() const { return data_.opcode_value; }
 
  bool IsPredicated() const { return data_.is_predicated; }
  bool GetPredicateCondition() const { return data_.pred_condition == 1; }
 
  u32 GetDest() const { return data_.dst_reg; }
  u32 GetDestSwizzle() const { return data_.dst_swiz; }
  bool IsDestRelative() const { return data_.dst_reg_am; }
  u32 GetSrcReg() const { return data_.src_reg; }
  bool IsSrcRelative() const { return data_.src_reg_am; }

  const VertexFetchInstruction& GetVertexFetch() const { return vertex_fetch_; }
  const TextureFetchInstruction& GetTextureFetch() const { return texture_fetch_; }
 
 private:
  struct Data {
    struct {
      FetchOpcode opcode_value : 5;
      u32 src_reg : 6;
      u32 src_reg_am : 1;
      u32 dst_reg : 6;
      u32 dst_reg_am : 1;
      u32 : 1;
      u32 const_index : 5; 
      u32 : 7;
    };
    struct {
      u32 dst_swiz : 12;
      u32 : 19;
      u32 is_predicated : 1;
    };
    struct {
      u32 : 31;
      u32 pred_condition : 1;
    };
  };
  Data data_;
  VertexFetchInstruction vertex_fetch_;
  TextureFetchInstruction texture_fetch_;
};
REX_STATIC_ASSERT_SIZE(FetchInstruction, sizeof(u32) * 3);

enum AluOpChangedState : u8 {
  kAluOpChangedStateNone = 0,
  kAluOpChangedStateAddressRegister = 1 << 0,
  kAluOpChangedStatePredicate = 1 << 1,
  kAluOpChangedStatePixelKill = 1 << 2,
};

// NOLINTNEXTLINE(performance-enum-size): Xenos bit field, MSVC packs per type
enum class AluScalarOpcode : u32 {
  kAdds = 0,

  kAddsPrev = 1,

  kMuls = 2,

  kMulsPrev = 3,

  kMulsPrev2 = 4,

  kMaxs = 5,

  kMins = 6,

  kSeqs = 7,

  kSgts = 8,

  kSges = 9,

  kSnes = 10,

  kFrcs = 11,

  kTruncs = 12,

  kFloors = 13,

  kExp = 14,

  kLogc = 15,

  kLog = 16,

  kRcpc = 17,

  kRcpf = 18,

  kRcp = 19,

  kRsqc = 20,

  kRsqf = 21,

  kRsq = 22,

  kMaxAs = 23,

  kMaxAsf = 24,

  kSubs = 25,

  kSubsPrev = 26,

  kSetpEq = 27,

  kSetpNe = 28,

  kSetpGt = 29,

  kSetpGe = 30,

  kSetpInv = 31,

  kSetpPop = 32,

  kSetpClr = 33,

  kSetpRstr = 34,

  kKillsEq = 35,

  kKillsGt = 36,

  kKillsGe = 37,

  kKillsNe = 38,

  kKillsOne = 39,

  kSqrt = 40,

  kMulsc0 = 42,
  kMulsc1 = 43,
  kAddsc0 = 44,
  kAddsc1 = 45,
  kSubsc0 = 46,
  kSubsc1 = 47,

  kSin = 48,

  kCos = 49,

  kRetainPrev = 50,
};
 
struct AluScalarOpcodeTraits {
  const char* name; 
  u32 operand_count;
  bool single_operand_is_two_component;
  AluOpChangedState changed_state;
};

extern const AluScalarOpcodeTraits kAluScalarOpcodeTraits[64];

inline const AluScalarOpcodeTraits& GetAluScalarOpcodeTraits(AluScalarOpcode opcode) {
  REX_ASSERT(static_cast<u32>(opcode) < rex::CountOf(kAluScalarOpcodeTraits));
  return kAluScalarOpcodeTraits[static_cast<u32>(opcode)];
}
 
// NOLINTNEXTLINE(performance-enum-size): Xenos bit field, MSVC packs per type
enum class AluVectorOpcode : u32 {
  kAdd = 0,

  kMul = 1,

  kMax = 2,

  kMin = 3,

  kSeq = 4,

  kSgt = 5,

  kSge = 6,

  kSne = 7,

  kFrc = 8,

  kTrunc = 9,

  kFloor = 10,

  kMad = 11,

  kCndEq = 12,

  kCndGe = 13,

  kCndGt = 14,

  kDp4 = 15,

  kDp3 = 16,

  kDp2Add = 17,

  kCube = 18,

  kMax4 = 19,

  kSetpEqPush = 20,

  kSetpNePush = 21,

  kSetpGtPush = 22,

  kSetpGePush = 23,

  kKillEq = 24,

  kKillGt = 25,

  kKillGe = 26,

  kKillNe = 27,

  kDst = 28,

  kMaxA = 29,
};
 
struct AluVectorOpcodeTraits {
  const char* name; 
  u32 operand_components_used[3];
  AluOpChangedState changed_state;

  u32 GetOperandCount() const {
    if (!operand_components_used[2]) {
      if (!operand_components_used[1]) {
        if (!operand_components_used[0]) {
          return 0;
        }
        return 1;
      }
      return 2;
    }
    return 3;
  }
};

extern const AluVectorOpcodeTraits kAluVectorOpcodeTraits[32];

inline const AluVectorOpcodeTraits& GetAluVectorOpcodeTraits(AluVectorOpcode opcode) {
  REX_ASSERT(static_cast<u32>(opcode) < rex::CountOf(kAluVectorOpcodeTraits));
  return kAluVectorOpcodeTraits[static_cast<u32>(opcode)];
}

inline u32 GetAluVectorOpNeededSourceComponents(AluVectorOpcode vector_opcode, u32 src_index,
                                                u32 used_result_components) {
  REX_ASSERT(src_index != 0);
  REX_ASSERT((used_result_components & ~static_cast<u32>(0b1111)) == 0);
  u32 components = used_result_components;
  switch (vector_opcode) {
    case AluVectorOpcode::kDp4:
    case AluVectorOpcode::kMax4:
      components = used_result_components ? 0b1111 : 0;
      break;
    case AluVectorOpcode::kDp3:
      components = used_result_components ? 0b0111 : 0;
      break;
    case AluVectorOpcode::kDp2Add:
      components = used_result_components ? (src_index == 3 ? 0b0001 : 0b0011) : 0;
      break;
    case AluVectorOpcode::kCube:
      components = used_result_components ? 0b1111 : 0;
      break;
    case AluVectorOpcode::kSetpEqPush:
    case AluVectorOpcode::kSetpNePush:
    case AluVectorOpcode::kSetpGtPush:
    case AluVectorOpcode::kSetpGePush:
      components = used_result_components ? 0b1001 : 0b1000;
      break;
    case AluVectorOpcode::kKillEq:
    case AluVectorOpcode::kKillGt:
    case AluVectorOpcode::kKillGe:
    case AluVectorOpcode::kKillNe:
      components = 0b1111;
      break;
    case AluVectorOpcode::kMaxA:
      if (src_index == 1) {
        components |= 0b1000;
      }
      break;
    default:
      break;
  }
  return components &
         GetAluVectorOpcodeTraits(vector_opcode).operand_components_used[src_index - 1];
}

constexpr u32 kMaxMemExportElementCount = 5;

enum class ExportRegister : u8 {
  kVSInterpolator0 = 0,
  kVSInterpolator1,
  kVSInterpolator2,
  kVSInterpolator3,
  kVSInterpolator4,
  kVSInterpolator5,
  kVSInterpolator6,
  kVSInterpolator7,
  kVSInterpolator8,
  kVSInterpolator9,
  kVSInterpolator10,
  kVSInterpolator11,
  kVSInterpolator12,
  kVSInterpolator13,
  kVSInterpolator14,
  kVSInterpolator15,

  kVSPosition = 62,

  kVSPointSizeEdgeFlagKillVertex = 63,

  kPSColor0 = 0,
  kPSColor1,
  kPSColor2,
  kPSColor3,

  kPSDepth = 61,
 
  kExportAddress = 32,
  kExportData0 = 33,
  kExportData1,
  kExportData2,
  kExportData3,
  kExportData4,
};

struct alignas(u32) AluInstruction {
  bool IsExport() const { return data_.export_data == 1; }
 
  bool IsPredicated() const { return data_.is_predicated; }
  bool GetPredicateCondition() const { return data_.pred_condition == 1; }

  bool HasAbsConstants() const { return data_.abs_constants == 1; }
  bool IsConst0Addressed() const { return data_.const_0_rel_abs == 1; }
  bool IsConst1Addressed() const { return data_.const_1_rel_abs == 1; }
  bool IsConstAddressRegisterRelative() const { return data_.const_address_register_relative == 1; }
 
  AluVectorOpcode GetVectorOpcode() const { return data_.vector_opc; }
  u32 GetVectorWriteMask() const { return data_.vector_write_mask; }
  u32 GetVectorDest() const { return data_.vector_dest; }
  bool IsVectorDestRelative() const { return data_.vector_dest_rel == 1; }
  bool IsVectorClamped() const { return data_.vector_clamp == 1; }
 
  AluScalarOpcode GetScalarOpcode() const { return data_.scalar_opc; }
  u32 GetScalarWriteMask() const { return data_.scalar_write_mask; }
  u32 GetScalarDest() const { return data_.scalar_dest; }
  bool IsScalarDestRelative() const { return data_.scalar_dest_rel == 1; }
  bool IsScalarClamped() const { return data_.scalar_clamp == 1; }

  static constexpr u32 GetSrcTempReg(u32 src_reg) { return src_reg & 0x3F; }
  static constexpr bool IsSrcTempRelative(u32 src_reg) { return (src_reg & 0x40) != 0; }
  static constexpr bool IsSrcTempValueAbsolute(u32 src_reg) { return (src_reg & 0x80) != 0; }
  u32 GetSrcReg(size_t i) const {
    switch (i) {
      case 1:
        return data_.src1_reg;
      case 2:
        return data_.src2_reg;
      case 3:
        return data_.src3_reg;
      default:
        REX_UNHANDLED_CASE(i);
        return 0;
    }
  }

  bool IsSrcTemp(size_t i) const {
    switch (i) {
      case 1:
        return static_cast<bool>(data_.src1_sel);
      case 2:
        return static_cast<bool>(data_.src2_sel);
      case 3:
        return static_cast<bool>(data_.src3_sel);
      default:
        REX_UNHANDLED_CASE(i);
        return 0;
    }
  }

  bool IsSrcConstAddressed(size_t i) const {
    switch (i) {
      case 1:
        return static_cast<bool>(data_.const_0_rel_abs);
      case 2:
        return static_cast<bool>(IsSrcTemp(1) ? data_.const_0_rel_abs : data_.const_1_rel_abs);
      case 3:
        return static_cast<bool>((IsSrcTemp(1) && IsSrcTemp(2)) ? data_.const_0_rel_abs
                                                                : data_.const_1_rel_abs);
      default:
        REX_UNHANDLED_CASE(i);
        return false;
    }
  }

  u32 GetSrcSwizzle(size_t i) const {
    switch (i) {
      case 1:
        return data_.src1_swiz;
      case 2:
        return data_.src2_swiz;
      case 3:
        return data_.src3_swiz;
      default:
        REX_UNHANDLED_CASE(i);
        return 0;
    }
  }

  bool IsSrcNegated(size_t i) const {
    switch (i) {
      case 1:
        return data_.src1_reg_negate == 1;
      case 2:
        return data_.src2_reg_negate == 1;
      case 3:
        return data_.src3_reg_negate == 1;
      default:
        REX_UNHANDLED_CASE(i);
        return 0;
    }
  }

  u32 GetScalarConstRegOpSrcTempReg() const {
    return (static_cast<u32>(data_.scalar_opc) & 1) | (data_.src3_sel << 1) |
           (data_.src3_swiz & 0x3C);
  }

  static constexpr u32 GetSwizzledComponentIndex(u32 swizzle, u32 component_index) {
    return ((swizzle >> (2 * component_index)) + component_index) & 3;
  }

  u32 GetVectorOpResultWriteMask() const {
    u32 mask = GetVectorWriteMask();
    if (IsExport()) {
      mask &= ~GetScalarWriteMask();
    }
    return mask;
  }

  u32 GetScalarOpResultWriteMask() const {
    u32 mask = GetScalarWriteMask();
    if (IsExport()) {
      mask &= ~GetVectorWriteMask();
    }
    return mask;
  }

  u32 GetConstant0WriteMask() const {
    if (!IsExport() || !IsScalarDestRelative()) {
      return 0b0000;
    }
    return 0b1111 & ~(GetVectorWriteMask() | GetScalarWriteMask());
  }

  u32 GetConstant1WriteMask() const {
    if (!IsExport()) {
      return 0b0000;
    }
    return GetVectorWriteMask() & GetScalarWriteMask();
  }
 
 private:
  struct Data {
    struct {
      u32 vector_dest : 6;
      u32 vector_dest_rel : 1;
      u32 abs_constants : 1;
      u32 scalar_dest : 6;
      u32 scalar_dest_rel : 1;
      u32 export_data : 1;
      u32 vector_write_mask : 4;
      u32 scalar_write_mask : 4;
      u32 vector_clamp : 1;
      u32 scalar_clamp : 1;
      AluScalarOpcode scalar_opc : 6;
    };
    struct {
      u32 src3_swiz : 8; 
      u32 src2_swiz : 8;
      u32 src1_swiz : 8;
      u32 src3_reg_negate : 1;
      u32 src2_reg_negate : 1;
      u32 src1_reg_negate : 1;
      u32 pred_condition : 1;
      u32 is_predicated : 1;
      u32 const_address_register_relative : 1;
      u32 const_1_rel_abs : 1;
      u32 const_0_rel_abs : 1;
    };
    struct {
      u32 src3_reg : 8;
      u32 src2_reg : 8;
      u32 src1_reg : 8;
      AluVectorOpcode vector_opc : 5;
      u32 src3_sel : 1; 
      u32 src2_sel : 1;
      u32 src1_sel : 1;
    };
  };
  Data data_;
};
REX_STATIC_ASSERT_SIZE(AluInstruction, sizeof(u32) * 3);
 
}  // namespace rex::xenos::ucode