Functions
simde__m128	ReciprocalEstimate (simde__m128 v) noexcept
simde__m128	ReciprocalSqrtEstimate (simde__m128 v) noexcept
simde__m128	Log2Estimate (simde__m128 v) noexcept
simde__m128	Exp2Estimate (simde__m128 v) noexcept
template<bool NonJava>
simde__m128	ReciprocalEstimate (simde__m128 v) noexcept
simde__m128	ReciprocalEstimate (simde__m128 v, bool non_java) noexcept
template<bool NonJava>
simde__m128	ReciprocalSqrtEstimate (simde__m128 v) noexcept
simde__m128	ReciprocalSqrtEstimate (simde__m128 v, bool non_java) noexcept
template<bool NonJava>
simde__m128	Log2Estimate (simde__m128 v) noexcept
simde__m128	Log2Estimate (simde__m128 v, bool non_java) noexcept
simde__m128	Exp2Estimate (simde__m128 v, bool non_java) noexcept
simde__m128	DotProduct3 (simde__m128 a, simde__m128 b) noexcept
simde__m128	DotProduct3 (simde__m128 a, simde__m128 b, bool non_java) noexcept
simde__m128	DotProduct4 (simde__m128 a, simde__m128 b) noexcept
simde__m128	DotProduct4 (simde__m128 a, simde__m128 b, bool non_java) noexcept
simde__m128	MultiplyAdd (simde__m128 a, simde__m128 b, simde__m128 c) noexcept
simde__m128	MultiplyAdd (simde__m128 a, simde__m128 b, simde__m128 c, bool non_java) noexcept
simde__m128	NegativeMultiplySubtract (simde__m128 a, simde__m128 b, simde__m128 c) noexcept
simde__m128	NegativeMultiplySubtract (simde__m128 a, simde__m128 b, simde__m128 c, bool non_java) noexcept
template<bool Signed>
bool	IsConvertSaturating (simde__m128 scaled) noexcept
template<u32 Bits, bool Signed>
bool	IsAddSaturating (simde__m128i a, simde__m128i b) noexcept
template<u32 Bits, bool Signed>
bool	IsSubSaturating (simde__m128i a, simde__m128i b) noexcept
template<u32 SourceBits, bool SignedDest>
bool	IsPackSaturating (simde__m128i a, simde__m128i b) noexcept
template<u32 Type>
bool	IsPackD3DSaturating (simde__m128 source) noexcept
template<u32 Type, u32 Mask, u32 Shift>
u8	PackD3D (VRegister &dest, const VRegister &source)

Variables
constexpr u32	kReciprocalBase [32]
constexpr i32	kReciprocalSlope [32]
constexpr u32	kReciprocalSqrtBase [32]
constexpr i32	kReciprocalSqrtSlope [32]
constexpr i32	kLog2Base [16]
constexpr i32	kLog2Slope [16]
constexpr u16	kExp2Positive [2048]
template<typename T>
using	VectorOf = std::conditional_t<std::is_floating_point_v<T>, simde__m128, simde__m128i>
constexpr u8	kVectorMaskL []
constexpr u8	kVectorMaskR []
constexpr u8	kVectorShiftTableL []
constexpr u8	kVectorShiftTableR []
template<typename T>
simde__m128i	AddSaturate (simde__m128i a, simde__m128i b)
template<>
simde__m128i	AddSaturate< u32 > (simde__m128i a, simde__m128i b)
template<typename T>
simde__m128i	Average (simde__m128i a, simde__m128i b)
template<>
simde__m128i	Average< i8 > (simde__m128i a, simde__m128i b)
template<>
simde__m128i	Average< i16 > (simde__m128i a, simde__m128i b)
template<>
simde__m128i	Average< i32 > (simde__m128i a, simde__m128i b)
template<typename To, typename From>
VectorOf< To >	Convert (VectorOf< From > src)
template<>
simde__m128	Convert< f32, u32 > (simde__m128i src1)
simde__m128i	PermuteBytes (simde__m128i a, simde__m128i b, simde__m128i c)
template<typename T>
simde__m128i	CompareGreater (simde__m128i a, simde__m128i b)
template<>
simde__m128i	CompareGreater< u8 > (simde__m128i a, simde__m128i b)
template<>
simde__m128i	CompareGreater< u16 > (simde__m128i a, simde__m128i b)
template<typename To, typename From>
VectorOf< To >	ConvertSaturate (VectorOf< From > src)
template<>
simde__m128i	ConvertSaturate< i32, f32 > (simde__m128 src1)
template<>
simde__m128i	ConvertSaturate< u32, f32 > (simde__m128 src1)
simde__m128i	ShiftRightBits (simde__m128i a, simde__m128i b)
simde__m128i	ShiftLeftBits (simde__m128i a, simde__m128i b)
simde__m128i	ShiftLeftBytes (simde__m128i a, simde__m128i b)
simde__m128i	ShiftRightBytes (simde__m128i a, simde__m128i b)
template<typename T>
simde__m128i	ShiftLeftLanes (simde__m128i a, simde__m128i count)
template<>
simde__m128i	ShiftLeftLanes< u16 > (simde__m128i a, simde__m128i count)
template<typename T>
simde__m128i	ShiftRightLanes (simde__m128i a, simde__m128i count)
template<>
simde__m128i	ShiftRightLanes< u16 > (simde__m128i a, simde__m128i count)
template<>
simde__m128i	ShiftRightLanes< i16 > (simde__m128i a, simde__m128i count)
template<>
simde__m128i	ShiftLeftLanes< u8 > (simde__m128i a, simde__m128i count)
simde__m128i	ToGuestByteOrder (simde__m128i v)
void	StoreVectorBytes (u8 host, const u8 bytes, u32 count)
void	StoreVectorLeft (u8 *host, u32 ea, simde__m128i v)
void	StoreVectorRight (u8 *host, u32 ea, simde__m128i v)
void	StoreVectorPair (u8 left_host, u32 left_ea, u8 right_host, u32 right_ea, simde__m128i v)

Detailed Description

The vector intrinsics that generated code uses.

Typedef Documentation

◆ VectorOf

template<typename T>

using rex::ppc::simd::VectorOf = std::conditional_t<std::is_floating_point_v<T>, simde__m128, simde__m128i>

Tables for the lvlx, lvrx, stvlx and stvrx vector load and store instructions, 16 rows of 16 bytes indexed by the low 4 address bits.

Function Documentation

◆ AddSaturate()

template<typename T>

simde__m128i rex::ppc::simd::AddSaturate	(	simde__m128i	a,
		simde__m128i	b )

Adds the lanes of two vectors with saturation.

◆ AddSaturate< u32 >()

template<>

simde__m128i rex::ppc::simd::AddSaturate< u32 >	(	simde__m128i	a,
		simde__m128i	b )

inline

Adds unsigned 32 bit lanes with saturation.

◆ Average()

template<typename T>

simde__m128i rex::ppc::simd::Average	(	simde__m128i	a,
		simde__m128i	b )

Averages the lanes of two vectors.

◆ Average< i16 >()

template<>

simde__m128i rex::ppc::simd::Average< i16 >	(	simde__m128i	a,
		simde__m128i	b )

inline

Averages signed 16 bit lanes.

◆ Average< i32 >()

template<>

simde__m128i rex::ppc::simd::Average< i32 >	(	simde__m128i	a,
		simde__m128i	b )

inline

Averages signed 32 bit lanes.

◆ Average< i8 >()

template<>

simde__m128i rex::ppc::simd::Average< i8 >	(	simde__m128i	a,
		simde__m128i	b )

inline

Averages signed 8 bit lanes, rounding toward positive infinity.

◆ CompareGreater()

template<typename T>

simde__m128i rex::ppc::simd::CompareGreater	(	simde__m128i	a,
		simde__m128i	b )

Compares the lanes of two vectors for greater than.

Returns: All ones in lanes where a is greater than b.

◆ CompareGreater< u16 >()

template<>

simde__m128i rex::ppc::simd::CompareGreater< u16 >	(	simde__m128i	a,
		simde__m128i	b )

inline

Compares unsigned 16 bit lanes for greater than.

Returns: All ones in lanes where a is greater than b.

◆ CompareGreater< u8 >()

template<>

simde__m128i rex::ppc::simd::CompareGreater< u8 >	(	simde__m128i	a,
		simde__m128i	b )

inline

Compares unsigned 8 bit lanes for greater than.

Returns: All ones in lanes where a is greater than b.

◆ Convert()

template<typename To, typename From>

VectorOf< To > rex::ppc::simd::Convert ( VectorOf< From > src )

Converts the lanes of a vector to another lane type.

◆ Convert< f32, u32 >()

template<>

simde__m128 rex::ppc::simd::Convert< f32, u32 > ( simde__m128i src1 )

inline

Converts unsigned 32 bit integers to floats.

◆ ConvertSaturate()

template<typename To, typename From>

VectorOf< To > rex::ppc::simd::ConvertSaturate ( VectorOf< From > src )

Converts the lanes of a vector to another lane type with saturation.

◆ ConvertSaturate< i32, f32 >()

template<>

simde__m128i rex::ppc::simd::ConvertSaturate< i32, f32 > ( simde__m128 src1 )

inline

Converts floats to signed fixed point words with saturation (vctsxs).

◆ ConvertSaturate< u32, f32 >()

template<>

simde__m128i rex::ppc::simd::ConvertSaturate< u32, f32 > ( simde__m128 src1 )

inline

Converts floats to unsigned fixed point words with saturation (vctuxs).

NaN and negative inputs give 0 and inputs above UINT_MAX give UINT_MAX.

Returns: The words, saturated to [0, UINT_MAX].

◆ DotProduct3() [1/2]

simde__m128 rex::ppc::simd::DotProduct3	(	simde__m128	a,
		simde__m128	b )

inlinenodiscardnoexcept

Computes vmsum3fp128, the dot product of the first 3 vector elements.

Returns: The dot product in all 4 lanes.

◆ DotProduct3() [2/2]

simde__m128 rex::ppc::simd::DotProduct3	(	simde__m128	a,
		simde__m128	b,
		bool	non_java )

inlinenodiscardnoexcept

Computes vmsum3fp128, the dot product of the first 3 elements, honoring VSCR NJ.

Parameters

non_java The VSCR NJ bit. When clear a denormal operand keeps its value.

Returns: The dot product in all 4 lanes.

◆ DotProduct4() [1/2]

simde__m128 rex::ppc::simd::DotProduct4	(	simde__m128	a,
		simde__m128	b )

inlinenodiscardnoexcept

Computes vmsum4fp128, the dot product of all 4 vector elements.

Returns: The dot product in all 4 lanes.

◆ DotProduct4() [2/2]

simde__m128 rex::ppc::simd::DotProduct4	(	simde__m128	a,
		simde__m128	b,
		bool	non_java )

inlinenodiscardnoexcept

Computes vmsum4fp128, the dot product of all 4 elements, honoring VSCR NJ.

Parameters

non_java The VSCR NJ bit. When clear a denormal operand keeps its value.

Returns: The dot product in all 4 lanes.

◆ Exp2Estimate() [1/2]

simde__m128 rex::ppc::simd::Exp2Estimate ( simde__m128 v )

inlinenodiscardnoexcept

Computes vexptefp and vexptefp128.

Returns: The exp2 estimate of each lane.

◆ Exp2Estimate() [2/2]

simde__m128 rex::ppc::simd::Exp2Estimate	(	simde__m128	v,
		bool	non_java )

inlinenodiscardnoexcept

Computes vexptefp and vexptefp128. A denormal operand gives 1.0 for either NJ value.

Parameters

non_java The VSCR NJ bit.

Returns: The exp2 estimate of each lane.

◆ IsAddSaturating()

template<u32 Bits, bool Signed>

bool rex::ppc::simd::IsAddSaturating	(	simde__m128i	a,
		simde__m128i	b )

inlinenodiscardnoexcept

Reports whether a saturating vector add clamps any lane.

Template Parameters

Bits	The element width, 8, 16 or 32.
Signed	True for the signed forms, false for the unsigned ones.

Returns: True when a lane overflows its element range.

◆ IsConvertSaturating()

template<bool Signed>

bool rex::ppc::simd::IsConvertSaturating ( simde__m128 scaled )

inlinenodiscardnoexcept

Reports whether a float to fixed point conversion clamps any lane, not counting a NaN lane.

Template Parameters

Signed True for the signed word conversion, false for the unsigned one.

Parameters

scaled The floats after the scale multiply.

Returns: True when a lane lies outside the range of the destination word.

◆ IsPackD3DSaturating()

template<u32 Type>

bool rex::ppc::simd::IsPackD3DSaturating ( simde__m128 source )

inlinenodiscardnoexcept

Reports whether a vpkd3d128 pack saturates. Every vector element counts, whatever the mask and shift write, and a NaN element never saturates.

Template Parameters

Type	The pack format, 0 to 6.

Returns: True when an element lies outside the range of its packed field.

◆ IsPackSaturating()

template<u32 SourceBits, bool SignedDest>

bool rex::ppc::simd::IsPackSaturating	(	simde__m128i	a,
		simde__m128i	b )

inlinenodiscardnoexcept

Reports whether a saturating vector pack clamps any lane of its two operands.

Template Parameters

SourceBits	The source element width, 16 or 32.
SignedDest	True when the packed elements are signed.

Returns: True when a source element lies outside the range of the packed element.

◆ IsSubSaturating()

template<u32 Bits, bool Signed>

bool rex::ppc::simd::IsSubSaturating	(	simde__m128i	a,
		simde__m128i	b )

inlinenodiscardnoexcept

Reports whether a saturating vector subtract clamps any lane.

Template Parameters

Bits	The element width, 8, 16 or 32.
Signed	True for the signed forms, false for the unsigned ones.

Parameters

a	The minuend.
b	The subtrahend.

Returns: True when a lane overflows its element range.

◆ Log2Estimate() [1/3]

template<bool NonJava>

simde__m128 rex::ppc::simd::Log2Estimate ( simde__m128 v )

inlinenodiscardnoexcept

Computes vlogefp and vlogefp128 for a fixed VSCR NJ bit.

Template Parameters

NonJava The VSCR NJ bit.

◆ Log2Estimate() [2/3]

simde__m128 rex::ppc::simd::Log2Estimate ( simde__m128 v )

inlinenodiscardnoexcept

Computes vlogefp and vlogefp128.

Returns: The log2 estimate of each lane.

◆ Log2Estimate() [3/3]

simde__m128 rex::ppc::simd::Log2Estimate	(	simde__m128	v,
		bool	non_java )

inlinenodiscardnoexcept

Computes vlogefp and vlogefp128, honoring VSCR NJ.

With NJ clear a denormal operand is estimated at its value.

Parameters

non_java The VSCR NJ bit.

Returns: The log2 estimate of each lane.

◆ MultiplyAdd() [1/2]

simde__m128 rex::ppc::simd::MultiplyAdd	(	simde__m128	a,
		simde__m128	b,
		simde__m128	c )

inlinenodiscardnoexcept

Computes vmaddfp, vmaddfp128 and vmaddcfp128 with a single rounding.

Returns: a * b + c in each lane.

◆ MultiplyAdd() [2/2]

simde__m128 rex::ppc::simd::MultiplyAdd	(	simde__m128	a,
		simde__m128	b,
		simde__m128	c,
		bool	non_java )

inlinenodiscardnoexcept

Computes vmaddfp, vmaddfp128 and vmaddcfp128 with a single rounding, honoring VSCR NJ.

Parameters

non_java The VSCR NJ bit. When clear a denormal operand and a denormal result are kept.

Returns: a * b + c in each lane.

◆ NegativeMultiplySubtract() [1/2]

simde__m128 rex::ppc::simd::NegativeMultiplySubtract	(	simde__m128	a,
		simde__m128	b,
		simde__m128	c )

inlinenodiscardnoexcept

Computes vnmsubfp and vnmsubfp128 with a single rounding.

Parameters

c	The value subtracted from the product.

Returns: -(a * b - c) in each lane.

◆ NegativeMultiplySubtract() [2/2]

simde__m128 rex::ppc::simd::NegativeMultiplySubtract	(	simde__m128	a,
		simde__m128	b,
		simde__m128	c,
		bool	non_java )

inlinenodiscardnoexcept

Computes vnmsubfp and vnmsubfp128 with a single rounding, honoring VSCR NJ.

Parameters

c	The value subtracted from the product.
non_java	The VSCR NJ bit. When clear a denormal operand and a denormal result are kept.

Returns: -(a * b - c) in each lane.

◆ PackD3D()

template<u32 Type, u32 Mask, u32 Shift>

u8 rex::ppc::simd::PackD3D	(	VRegister &	dest,
		const VRegister &	source )

inline

Packs a vector the way vpkd3d128 does. Element 0 is word index 3 of the register, and dest may be source.

Template Parameters

Type	The pack format, 0 to 6.
Mask	The vpkd3d128 mask, 0 to 3.
Shift	The vpkd3d128 shift, 0 to 3.

Returns: 1 when an element lay outside the range of its field, otherwise 0.

◆ PermuteBytes()

simde__m128i rex::ppc::simd::PermuteBytes	(	simde__m128i	a,
		simde__m128i	b,
		simde__m128i	c )

inline

Tables for the lvlx, lvrx, stvlx and stvrx vector load and store instructions, 16 rows of 16 bytes indexed by the low 4 address bits.

◆ ReciprocalEstimate() [1/3]

template<bool NonJava>

simde__m128 rex::ppc::simd::ReciprocalEstimate ( simde__m128 v )

inlinenodiscardnoexcept

Computes vrefp and vrefp128 for a fixed VSCR NJ bit.

Template Parameters

NonJava The VSCR NJ bit.

◆ ReciprocalEstimate() [2/3]

simde__m128 rex::ppc::simd::ReciprocalEstimate ( simde__m128 v )

inlinenodiscardnoexcept

Computes vrefp and vrefp128.

◆ ReciprocalEstimate() [3/3]

simde__m128 rex::ppc::simd::ReciprocalEstimate	(	simde__m128	v,
		bool	non_java )

inlinenodiscardnoexcept

Computes vrefp and vrefp128, honoring VSCR NJ.

With NJ clear, denormal operands and results are kept, rounded to nearest even.

Parameters

non_java The VSCR NJ bit.

◆ ReciprocalSqrtEstimate() [1/3]

template<bool NonJava>

simde__m128 rex::ppc::simd::ReciprocalSqrtEstimate ( simde__m128 v )

inlinenodiscardnoexcept

Computes vrsqrtefp and vrsqrtefp128 for a fixed VSCR NJ bit.

Template Parameters

NonJava The VSCR NJ bit.

◆ ReciprocalSqrtEstimate() [2/3]

simde__m128 rex::ppc::simd::ReciprocalSqrtEstimate ( simde__m128 v )

inlinenodiscardnoexcept

Computes vrsqrtefp and vrsqrtefp128.

Returns: The reciprocal square root estimate of each lane.

◆ ReciprocalSqrtEstimate() [3/3]

simde__m128 rex::ppc::simd::ReciprocalSqrtEstimate	(	simde__m128	v,
		bool	non_java )

inlinenodiscardnoexcept

Computes vrsqrtefp and vrsqrtefp128, honoring VSCR NJ.

With NJ clear a denormal operand is estimated at its value.

Parameters

non_java The VSCR NJ bit.

Returns: The reciprocal square root estimate of each lane.

◆ ShiftLeftBits()

simde__m128i rex::ppc::simd::ShiftLeftBits	(	simde__m128i	a,
		simde__m128i	b )

inline

Shifts the whole 128 bit vector left (vsl) by the low 3 bits of b.

Parameters

b	The shift count source, read from byte 15 which is byte 0 in big endian.

◆ ShiftLeftBytes()

simde__m128i rex::ppc::simd::ShiftLeftBytes	(	simde__m128i	a,
		simde__m128i	b )

inline

Shifts the whole vector left by bytes (vslo) given by bits [121:124] of b.

Parameters

b	The byte count source.

◆ ShiftLeftLanes()

template<typename T>

simde__m128i rex::ppc::simd::ShiftLeftLanes	(	simde__m128i	a,
		simde__m128i	count )

Shifts each lane left by the count in the same lane.

◆ ShiftLeftLanes< u16 >()

template<>

simde__m128i rex::ppc::simd::ShiftLeftLanes< u16 >	(	simde__m128i	a,
		simde__m128i	count )

inline

Shifts 16 bit lanes left by per lane counts.

◆ ShiftLeftLanes< u8 >()

template<>

simde__m128i rex::ppc::simd::ShiftLeftLanes< u8 >	(	simde__m128i	a,
		simde__m128i	count )

inline

Shifts 8 bit lanes left by per lane counts.

◆ ShiftRightBits()

simde__m128i rex::ppc::simd::ShiftRightBits	(	simde__m128i	a,
		simde__m128i	b )

inline

Shifts the whole 128 bit vector right (vsr).

Parameters

b	The shift count source.

◆ ShiftRightBytes()

simde__m128i rex::ppc::simd::ShiftRightBytes	(	simde__m128i	a,
		simde__m128i	b )

inline

Shifts the whole vector right by bytes (vsro) given by bits [121:124] of b.

Parameters

b	The byte count source.

◆ ShiftRightLanes()

template<typename T>

simde__m128i rex::ppc::simd::ShiftRightLanes	(	simde__m128i	a,
		simde__m128i	count )

Shifts each lane right by the count in the same lane. A signed lane type shifts arithmetically.

◆ ShiftRightLanes< i16 >()

template<>

simde__m128i rex::ppc::simd::ShiftRightLanes< i16 >	(	simde__m128i	a,
		simde__m128i	count )

inline

Shifts 16 bit lanes right arithmetically by per lane counts.

◆ ShiftRightLanes< u16 >()

template<>

simde__m128i rex::ppc::simd::ShiftRightLanes< u16 >	(	simde__m128i	a,
		simde__m128i	count )

inline

Shifts 16 bit lanes right logically by per lane counts.

◆ StoreVectorBytes()

void rex::ppc::simd::StoreVectorBytes	(	u8 *	host,
		const u8 *	bytes,
		u32	count )

inline

Writes the first count bytes of a 16 byte buffer to host memory, touching no other byte.

Parameters

bytes	The 16 byte source in guest memory order.
count	The number of bytes to write, 0 to 16.

◆ StoreVectorLeft()

void rex::ppc::simd::StoreVectorLeft	(	u8 *	host,
		u32	ea,
		simde__m128i	v )

inline

Stores the first 16 - (ea & 0xF) guest order bytes of a vector, the stvlx operation.

Parameters

host	The host address of ea.

◆ StoreVectorPair()

void rex::ppc::simd::StoreVectorPair	(	u8 *	left_host,
		u32	left_ea,
		u8 *	right_host,
		u32	right_ea,
		simde__m128i	v )

inline

Stores a vector with the stvlx and stvrx pair used for unaligned stores.

Parameters

left_host	The host address of the stvlx address.
left_ea	The stvlx guest effective address.
right_host	Host address of the start of the quadword containing the stvrx address.
right_ea	The stvrx guest effective address.

◆ StoreVectorRight()

void rex::ppc::simd::StoreVectorRight	(	u8 *	host,
		u32	ea,
		simde__m128i	v )

inline

Stores the last ea & 0xF guest order bytes of a vector at the start of the quadword that holds ea, the stvrx operation. Writes nothing when ea is aligned.

Parameters

host	The host address of the start of that quadword.

◆ ToGuestByteOrder()

simde__m128i rex::ppc::simd::ToGuestByteOrder ( simde__m128i v )

inline

Reverses the 16 bytes of a vector register into guest byte order.

Variable Documentation

◆ kExp2Positive

u16 rex::ppc::simd::kExp2Positive[2048]

inlineconstexpr

Top 11 mantissa bits of 2^x indexed by the 11 fraction bits of a positive operand.

◆ kLog2Base

i32 rex::ppc::simd::kLog2Base[16]

inlineconstexpr

Initial value:

                               = {
    0,    1536,  2816,  4096,  5248,  6400,  7552,  8576,
    9600, 10623, 11519, 12415, 13310, 14078, 14846, 15614,
}

Fraction base of the vector log2 estimate indexed by the top 4 mantissa bits.

◆ kLog2Slope

i32 rex::ppc::simd::kLog2Slope[16]

inlineconstexpr

Initial value:

                                = {
    12, 10, 10, 9, 9, 9, 8, 8, 8, 7, 7, 7, 6, 6, 6, 6,
}

Fraction slope of the vector log2 estimate indexed by the top 4 mantissa bits.

◆ kReciprocalBase

u32 rex::ppc::simd::kReciprocalBase[32]

inlineconstexpr

Initial value:

                                     = {
    0x7FF800, 0x783800, 0x70EA00, 0x6A0800, 0x638800, 0x5D6200, 0x579000, 0x520800,
    0x4CC800, 0x47CA00, 0x430800, 0x3E8000, 0x3A2C00, 0x360800, 0x321400, 0x2E4A00,
    0x2AA800, 0x272C00, 0x23D600, 0x209E00, 0x1D8800, 0x1A9000, 0x17AE00, 0x14F800,
    0x124400, 0x0FBE00, 0x0D3800, 0x0ADE00, 0x088400, 0x065000, 0x041C00, 0x020C00,
}

Mantissa base of the vector reciprocal estimate indexed by the top 5 mantissa bits.

◆ kReciprocalSlope

i32 rex::ppc::simd::kReciprocalSlope[32]

inlineconstexpr

Initial value:

                                      = {
    -3972, -3740, -3524, -3328, -3148, -2984, -2832, -2688, -2556, -2436, -2324,
    -2216, -2120, -2028, -1940, -1860, -1784, -1712, -1644, -1580, -1520, -1464,
    -1388, -1388, -1292, -1292, -1204, -1204, -1128, -1128, -1056, -1048,
}

Mantissa slope of the vector reciprocal estimate indexed by the top 5 mantissa bits.

◆ kReciprocalSqrtBase

u32 rex::ppc::simd::kReciprocalSqrtBase[32]

inlineconstexpr

Initial value:

                                         = {
    0x7FF400, 0x785200, 0x715400, 0x6AE400, 0x64F200, 0x5F6E00, 0x5A4C00, 0x558000,
    0x510200, 0x4CCA00, 0x48D000, 0x450E00, 0x418200, 0x3E2400, 0x3AF200, 0x37E800,
    0x34FD00, 0x2F9700, 0x2AA500, 0x261800, 0x21E400, 0x1DFE00, 0x1A5C00, 0x16F800,
    0x13CA00, 0x10CE00, 0x0DFE00, 0x0B5700, 0x08D400, 0x067300, 0x043100, 0x020B00,
}

Vector reciprocal square root mantissa base indexed by parity and the top 4 mantissa bits.

◆ kReciprocalSqrtSlope

i32 rex::ppc::simd::kReciprocalSqrtSlope[32]

inlineconstexpr

Initial value:

                                          = {
    -1956, -1792, -1648, -1522, -1412, -1316, -1228, -1150, -1082, -1018, -962,
    -910,  -862,  -818,  -778,  -742,  -1384, -1267, -1165, -1077, -999,  -930,
    -869,  -814,  -764,  -720,  -680,  -643,  -609,  -579,  -550,  -523,
}

Vector reciprocal square root mantissa slope indexed by parity and the top 4 mantissa bits.

◆ kVectorMaskL

u8 rex::ppc::simd::kVectorMaskL[]

inlineconstexpr

Initial value:

                                         = {
    0x0F, 0x0E, 0x0D, 0x0C, 0x0B, 0x0A, 0x09, 0x08, 0x07, 0x06, 0x05, 0x04, 0x03, 0x02, 0x01, 0x00,
    0xFF, 0x0F, 0x0E, 0x0D, 0x0C, 0x0B, 0x0A, 0x09, 0x08, 0x07, 0x06, 0x05, 0x04, 0x03, 0x02, 0x01,
    0xFF, 0xFF, 0x0F, 0x0E, 0x0D, 0x0C, 0x0B, 0x0A, 0x09, 0x08, 0x07, 0x06, 0x05, 0x04, 0x03, 0x02,
    0xFF, 0xFF, 0xFF, 0x0F, 0x0E, 0x0D, 0x0C, 0x0B, 0x0A, 0x09, 0x08, 0x07, 0x06, 0x05, 0x04, 0x03,
    0xFF, 0xFF, 0xFF, 0xFF, 0x0F, 0x0E, 0x0D, 0x0C, 0x0B, 0x0A, 0x09, 0x08, 0x07, 0x06, 0x05, 0x04,
    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x0F, 0x0E, 0x0D, 0x0C, 0x0B, 0x0A, 0x09, 0x08, 0x07, 0x06, 0x05,
    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x0F, 0x0E, 0x0D, 0x0C, 0x0B, 0x0A, 0x09, 0x08, 0x07, 0x06,
    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x0F, 0x0E, 0x0D, 0x0C, 0x0B, 0x0A, 0x09, 0x08, 0x07,
    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x0F, 0x0E, 0x0D, 0x0C, 0x0B, 0x0A, 0x09, 0x08,
    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x0F, 0x0E, 0x0D, 0x0C, 0x0B, 0x0A, 0x09,
    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x0F, 0x0E, 0x0D, 0x0C, 0x0B, 0x0A,
    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x0F, 0x0E, 0x0D, 0x0C, 0x0B,
    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x0F, 0x0E, 0x0D, 0x0C,
    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x0F, 0x0E, 0x0D,
    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x0F, 0x0E,
    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x0F,
}

Tables for the lvlx, lvrx, stvlx and stvrx vector load and store instructions, 16 rows of 16 bytes indexed by the low 4 address bits.

◆ kVectorMaskR

u8 rex::ppc::simd::kVectorMaskR[]

inlineconstexpr

Initial value:

                                         = {
    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
    0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
    0x01, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
    0x02, 0x01, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
    0x03, 0x02, 0x01, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
    0x04, 0x03, 0x02, 0x01, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
    0x05, 0x04, 0x03, 0x02, 0x01, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
    0x06, 0x05, 0x04, 0x03, 0x02, 0x01, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
    0x07, 0x06, 0x05, 0x04, 0x03, 0x02, 0x01, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
    0x08, 0x07, 0x06, 0x05, 0x04, 0x03, 0x02, 0x01, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
    0x09, 0x08, 0x07, 0x06, 0x05, 0x04, 0x03, 0x02, 0x01, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
    0x0A, 0x09, 0x08, 0x07, 0x06, 0x05, 0x04, 0x03, 0x02, 0x01, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
    0x0B, 0x0A, 0x09, 0x08, 0x07, 0x06, 0x05, 0x04, 0x03, 0x02, 0x01, 0x00, 0xFF, 0xFF, 0xFF, 0xFF,
    0x0C, 0x0B, 0x0A, 0x09, 0x08, 0x07, 0x06, 0x05, 0x04, 0x03, 0x02, 0x01, 0x00, 0xFF, 0xFF, 0xFF,
    0x0D, 0x0C, 0x0B, 0x0A, 0x09, 0x08, 0x07, 0x06, 0x05, 0x04, 0x03, 0x02, 0x01, 0x00, 0xFF, 0xFF,
    0x0E, 0x0D, 0x0C, 0x0B, 0x0A, 0x09, 0x08, 0x07, 0x06, 0x05, 0x04, 0x03, 0x02, 0x01, 0x00, 0xFF,
}

Tables for the lvlx, lvrx, stvlx and stvrx vector load and store instructions, 16 rows of 16 bytes indexed by the low 4 address bits.

◆ kVectorShiftTableL

u8 rex::ppc::simd::kVectorShiftTableL[]

inlineconstexpr

Initial value:

                                               = {
    0x0F, 0x0E, 0x0D, 0x0C, 0x0B, 0x0A, 0x09, 0x08, 0x07, 0x06, 0x05, 0x04, 0x03, 0x02, 0x01, 0x00,
    0x10, 0x0F, 0x0E, 0x0D, 0x0C, 0x0B, 0x0A, 0x09, 0x08, 0x07, 0x06, 0x05, 0x04, 0x03, 0x02, 0x01,
    0x11, 0x10, 0x0F, 0x0E, 0x0D, 0x0C, 0x0B, 0x0A, 0x09, 0x08, 0x07, 0x06, 0x05, 0x04, 0x03, 0x02,
    0x12, 0x11, 0x10, 0x0F, 0x0E, 0x0D, 0x0C, 0x0B, 0x0A, 0x09, 0x08, 0x07, 0x06, 0x05, 0x04, 0x03,
    0x13, 0x12, 0x11, 0x10, 0x0F, 0x0E, 0x0D, 0x0C, 0x0B, 0x0A, 0x09, 0x08, 0x07, 0x06, 0x05, 0x04,
    0x14, 0x13, 0x12, 0x11, 0x10, 0x0F, 0x0E, 0x0D, 0x0C, 0x0B, 0x0A, 0x09, 0x08, 0x07, 0x06, 0x05,
    0x15, 0x14, 0x13, 0x12, 0x11, 0x10, 0x0F, 0x0E, 0x0D, 0x0C, 0x0B, 0x0A, 0x09, 0x08, 0x07, 0x06,
    0x16, 0x15, 0x14, 0x13, 0x12, 0x11, 0x10, 0x0F, 0x0E, 0x0D, 0x0C, 0x0B, 0x0A, 0x09, 0x08, 0x07,
    0x17, 0x16, 0x15, 0x14, 0x13, 0x12, 0x11, 0x10, 0x0F, 0x0E, 0x0D, 0x0C, 0x0B, 0x0A, 0x09, 0x08,
    0x18, 0x17, 0x16, 0x15, 0x14, 0x13, 0x12, 0x11, 0x10, 0x0F, 0x0E, 0x0D, 0x0C, 0x0B, 0x0A, 0x09,
    0x19, 0x18, 0x17, 0x16, 0x15, 0x14, 0x13, 0x12, 0x11, 0x10, 0x0F, 0x0E, 0x0D, 0x0C, 0x0B, 0x0A,
    0x1A, 0x19, 0x18, 0x17, 0x16, 0x15, 0x14, 0x13, 0x12, 0x11, 0x10, 0x0F, 0x0E, 0x0D, 0x0C, 0x0B,
    0x1B, 0x1A, 0x19, 0x18, 0x17, 0x16, 0x15, 0x14, 0x13, 0x12, 0x11, 0x10, 0x0F, 0x0E, 0x0D, 0x0C,
    0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x17, 0x16, 0x15, 0x14, 0x13, 0x12, 0x11, 0x10, 0x0F, 0x0E, 0x0D,
    0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x17, 0x16, 0x15, 0x14, 0x13, 0x12, 0x11, 0x10, 0x0F, 0x0E,
    0x1E, 0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x17, 0x16, 0x15, 0x14, 0x13, 0x12, 0x11, 0x10, 0x0F,
}

Tables for the lvlx, lvrx, stvlx and stvrx vector load and store instructions, 16 rows of 16 bytes indexed by the low 4 address bits.

◆ kVectorShiftTableR

u8 rex::ppc::simd::kVectorShiftTableR[]

inlineconstexpr

Initial value:

                                               = {
    0x1F, 0x1E, 0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x17, 0x16, 0x15, 0x14, 0x13, 0x12, 0x11, 0x10,
    0x1E, 0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x17, 0x16, 0x15, 0x14, 0x13, 0x12, 0x11, 0x10, 0x0F,
    0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x17, 0x16, 0x15, 0x14, 0x13, 0x12, 0x11, 0x10, 0x0F, 0x0E,
    0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x17, 0x16, 0x15, 0x14, 0x13, 0x12, 0x11, 0x10, 0x0F, 0x0E, 0x0D,
    0x1B, 0x1A, 0x19, 0x18, 0x17, 0x16, 0x15, 0x14, 0x13, 0x12, 0x11, 0x10, 0x0F, 0x0E, 0x0D, 0x0C,
    0x1A, 0x19, 0x18, 0x17, 0x16, 0x15, 0x14, 0x13, 0x12, 0x11, 0x10, 0x0F, 0x0E, 0x0D, 0x0C, 0x0B,
    0x19, 0x18, 0x17, 0x16, 0x15, 0x14, 0x13, 0x12, 0x11, 0x10, 0x0F, 0x0E, 0x0D, 0x0C, 0x0B, 0x0A,
    0x18, 0x17, 0x16, 0x15, 0x14, 0x13, 0x12, 0x11, 0x10, 0x0F, 0x0E, 0x0D, 0x0C, 0x0B, 0x0A, 0x09,
    0x17, 0x16, 0x15, 0x14, 0x13, 0x12, 0x11, 0x10, 0x0F, 0x0E, 0x0D, 0x0C, 0x0B, 0x0A, 0x09, 0x08,
    0x16, 0x15, 0x14, 0x13, 0x12, 0x11, 0x10, 0x0F, 0x0E, 0x0D, 0x0C, 0x0B, 0x0A, 0x09, 0x08, 0x07,
    0x15, 0x14, 0x13, 0x12, 0x11, 0x10, 0x0F, 0x0E, 0x0D, 0x0C, 0x0B, 0x0A, 0x09, 0x08, 0x07, 0x06,
    0x14, 0x13, 0x12, 0x11, 0x10, 0x0F, 0x0E, 0x0D, 0x0C, 0x0B, 0x0A, 0x09, 0x08, 0x07, 0x06, 0x05,
    0x13, 0x12, 0x11, 0x10, 0x0F, 0x0E, 0x0D, 0x0C, 0x0B, 0x0A, 0x09, 0x08, 0x07, 0x06, 0x05, 0x04,
    0x12, 0x11, 0x10, 0x0F, 0x0E, 0x0D, 0x0C, 0x0B, 0x0A, 0x09, 0x08, 0x07, 0x06, 0x05, 0x04, 0x03,
    0x11, 0x10, 0x0F, 0x0E, 0x0D, 0x0C, 0x0B, 0x0A, 0x09, 0x08, 0x07, 0x06, 0x05, 0x04, 0x03, 0x02,
    0x10, 0x0F, 0x0E, 0x0D, 0x0C, 0x0B, 0x0A, 0x09, 0x08, 0x07, 0x06, 0x05, 0x04, 0x03, 0x02, 0x01,
}

Tables for the lvlx, lvrx, stvlx and stvrx vector load and store instructions, 16 rows of 16 bytes indexed by the low 4 address bits.

Functions

Variables

Detailed Description

Typedef Documentation

◆ VectorOf

Function Documentation

◆ AddSaturate()

◆ AddSaturate< u32 >()

◆ Average()

◆ Average< i16 >()

◆ Average< i32 >()

◆ Average< i8 >()

◆ CompareGreater()

◆ CompareGreater< u16 >()

◆ CompareGreater< u8 >()

◆ Convert()

◆ Convert< f32, u32 >()

◆ ConvertSaturate()

◆ ConvertSaturate< i32, f32 >()

◆ ConvertSaturate< u32, f32 >()

◆ DotProduct3() [1/2]

◆ DotProduct3() [2/2]

◆ DotProduct4() [1/2]

◆ DotProduct4() [2/2]

◆ Exp2Estimate() [1/2]

◆ Exp2Estimate() [2/2]

◆ IsAddSaturating()

◆ IsConvertSaturating()

◆ IsPackD3DSaturating()

◆ IsPackSaturating()

◆ IsSubSaturating()

◆ Log2Estimate() [1/3]

◆ Log2Estimate() [2/3]

◆ Log2Estimate() [3/3]

◆ MultiplyAdd() [1/2]

◆ MultiplyAdd() [2/2]

◆ NegativeMultiplySubtract() [1/2]

◆ NegativeMultiplySubtract() [2/2]

◆ PackD3D()

◆ PermuteBytes()

◆ ReciprocalEstimate() [1/3]

◆ ReciprocalEstimate() [2/3]

◆ ReciprocalEstimate() [3/3]

◆ ReciprocalSqrtEstimate() [1/3]

◆ ReciprocalSqrtEstimate() [2/3]

◆ ReciprocalSqrtEstimate() [3/3]

◆ ShiftLeftBits()

◆ ShiftLeftBytes()

◆ ShiftLeftLanes()

◆ ShiftLeftLanes< u16 >()

◆ ShiftLeftLanes< u8 >()

◆ ShiftRightBits()

◆ ShiftRightBytes()

◆ ShiftRightLanes()

◆ ShiftRightLanes< i16 >()

◆ ShiftRightLanes< u16 >()

◆ StoreVectorBytes()

◆ StoreVectorLeft()

◆ StoreVectorPair()

◆ StoreVectorRight()

◆ ToGuestByteOrder()

Variable Documentation

◆ kExp2Positive

◆ kLog2Base

◆ kLog2Slope

◆ kReciprocalBase

◆ kReciprocalSlope

◆ kReciprocalSqrtBase

◆ kReciprocalSqrtSlope

◆ kVectorMaskL

◆ kVectorMaskR

◆ kVectorShiftTableL

◆ kVectorShiftTableR