context.h

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/*
 * Parts of the PPCContext infrastructure are based on XenonRecomp and UnleashedRecomp.
 */
 
#pragma once
 
#include <atomic>
#include <bit>
#include <cmath>
#include <cstddef>
#include <cstdint>
#include <cstring>
#include <simde/x86/sse2.h>
 
#include <rex/ppc/recompiled_code.h>
#include <rex/types.h>
#include <rex/platform.h>
 
#ifndef _MM_DENORMALS_ZERO_MASK
#define _MM_DENORMALS_ZERO_MASK 0x0040
#endif
 
namespace rex::ppc {
 
#if defined(__x86_64__) || defined(_M_X64)

struct FPSCRPlatform {
  static constexpr size_t kRoundShift = 13;                    
  static constexpr size_t kRoundMaskVal = SIMDE_MM_ROUND_MASK; 
  static constexpr size_t kFlushMask = SIMDE_MM_FLUSH_ZERO_MASK | _MM_DENORMALS_ZERO_MASK;
  static constexpr u32 kExceptionMask =
      (1 << 7) | (1 << 8) | (1 << 9) | (1 << 10) | (1 << 11) | (1 << 12);
  static constexpr u32 kExceptionsMasked = kExceptionMask;
  static constexpr size_t kGuestToHost[] = {SIMDE_MM_ROUND_NEAREST, SIMDE_MM_ROUND_TOWARD_ZERO,
                                            SIMDE_MM_ROUND_UP, SIMDE_MM_ROUND_DOWN};
  static constexpr u32 kHostToGuest[] = {0, 3, 2, 1};

  static u32 GetCSR() noexcept { return simde_mm_getcsr(); }

  static void SetCSR(u32 csr) noexcept { simde_mm_setcsr(csr); }

  static void InitHostExceptions(u32& csr) noexcept { csr |= kExceptionMask; }
};
 
#elif defined(__aarch64__) || defined(_M_ARM64)

struct FPSCRPlatform {
  static constexpr size_t kRoundShift = 22;                 
  static constexpr size_t kRoundMaskVal = 3 << kRoundShift; 
  static constexpr size_t kFlushMask = 1 << 24;             
  static constexpr size_t kGuestToHost[] = {0 << kRoundShift, 3 << kRoundShift, 1 << kRoundShift,
                                            2 << kRoundShift};
  static constexpr u32 kHostToGuest[] = {0, 2, 3, 1};
  static constexpr u32 kExceptionMask =
      (1 << 8) | (1 << 9) | (1 << 10) | (1 << 11) | (1 << 12) | (1 << 15);
  static constexpr u32 kExceptionsMasked = 0;

  static inline u32 GetCSR() noexcept {
    u64 csr;
    __asm__ __volatile__("mrs %0, fpcr" : "=r"(csr));
    return static_cast<u32>(csr);
  }

  static inline void SetCSR(u32 csr) noexcept {
    __asm__ __volatile__("msr fpcr, %0" : : "r"(static_cast<u64>(csr)));
  }

  static inline void InitHostExceptions(u32& csr) noexcept { csr &= ~kExceptionMask; }
};
 
#else
#error "Missing implementation for FPSCR."
#endif
 
}  // namespace rex::ppc
 
namespace rex::kernel {
class ThreadState;
}  // namespace rex::kernel
 
namespace rex::ppc::detail {
struct DetourFrame;
}  // namespace rex::ppc::detail
 
namespace rex::ppc {
 
union Register {
  i8 s8;
  uint8_t u8;
  i16 s16;
  uint16_t u16;
  i32 s32;
  uint32_t u32;
  i64 s64;
  uint64_t u64;
  float f32;
  double f64;
};

struct XERRegister {
  u8 so; 
  u8 ov; 
  u8 ca; 
};

struct CRRegister {
  u8 lt; 
  u8 gt; 
  u8 eq; 
  union {
    u8 so; 
    u8 un; 
  };

  u32 GetRaw() const noexcept { return (lt << 3) | (gt << 2) | (eq << 1) | so; }

  void SetRaw(u32 value) noexcept {
    lt = (value >> 3) & 1;
    gt = (value >> 2) & 1;
    eq = (value >> 1) & 1;
    so = value & 1;
  }

  template <typename T>
  void Compare(T left, T right, const XERRegister& xer) noexcept {
    lt = left < right;
    gt = left > right;
    eq = left == right;
    so = xer.so;
  }

  void Compare(f64 left, f64 right) noexcept {
    un = std::isnan(left) || std::isnan(right);
    lt = !un && (left < right);
    gt = !un && (left > right);
    eq = !un && (left == right);
  }

  void SetFromMask(simde__m128 mask, int imm) noexcept {
    int m = simde_mm_movemask_ps(mask);
    lt = m == imm;
    gt = 0;
    eq = m == 0;
    so = 0;
  }

  void SetFromMask(simde__m128i mask, int imm) noexcept {
    int m = simde_mm_movemask_epi8(mask);
    lt = m == imm;
    gt = 0;
    eq = m == 0;
    so = 0;
  }
};
 
union alignas(0x10) VRegister {
  i8 s8[16];
  uint8_t u8[16];
  i16 s16[8];
  uint16_t u16[8];
  i32 s32[4];
  uint32_t u32[4];
  i64 s64[2];
  uint64_t u64[2];
  float f32[4];
  double f64[2];
};
 
constexpr u32 kRoundNearest = 0x00;
constexpr u32 kRoundTowardZero = 0x01;
constexpr u32 kRoundUp = 0x02;   
constexpr u32 kRoundDown = 0x03; 
constexpr u32 kRoundMask = 0x03;

struct FPSCRRegister {
  u32 csr; 

  using Platform = FPSCRPlatform;
  static constexpr size_t kRoundShift = Platform::kRoundShift;
  static constexpr size_t kRoundMaskVal = Platform::kRoundMaskVal;
  static constexpr size_t kFlushMask = Platform::kFlushMask;
 
  static_assert(
      [] {
        for (u32 rn = 0; rn <= kRoundMask; ++rn) {
          if (Platform::kHostToGuest[(Platform::kGuestToHost[rn] & kRoundMaskVal) >> kRoundShift] !=
              rn) {
            return false;
          }
        }
        return true;
      }(),
      "kHostToGuest must invert kGuestToHost");

  static constexpr u32 kGuestMask = static_cast<u32>(kRoundMaskVal) | static_cast<u32>(kFlushMask);

  u32 GetCSR() noexcept { return Platform::GetCSR(); }

  void SetCSR(u32 value) noexcept { Platform::SetCSR(value); }

  void RestoreGuestBits(u32 saved) noexcept {
    csr = (GetCSR() & ~kGuestMask) | (saved & kGuestMask);
    SetCSR(csr);
  }

  u32 LoadFromHost() noexcept {
    csr = GetCSR();
    return Platform::kHostToGuest[(csr & kRoundMaskVal) >> kRoundShift];
  }

  void StoreToHost(u32 value) noexcept {
    csr &= ~kRoundMaskVal;
    csr |= Platform::kGuestToHost[value & kRoundMask];
    SetCSR(csr);
  }

  void EnableFlushModeUnconditional() noexcept {
    csr |= kFlushMask;
    SetCSR(csr);
  }

  void DisableFlushModeUnconditional() noexcept {
    csr &= ~kFlushMask;
    SetCSR(csr);
  }

  void EnableFlushMode() noexcept {
    if ((csr & kFlushMask) != kFlushMask) [[unlikely]] {
      csr |= kFlushMask;
      SetCSR(csr);
    }
  }

  void DisableFlushMode() noexcept {
    if ((csr & kFlushMask) != 0) [[unlikely]] {
      csr &= ~kFlushMask;
      SetCSR(csr);
    }
  }

  void SetFlushMode(bool enable) noexcept {
    if (enable) {
      EnableFlushMode();
    } else {
      DisableFlushMode();
    }
  }

  void InitHost() noexcept {
    csr = GetCSR();
    Platform::InitHostExceptions(csr);
    SetCSR(csr);
  }
};

struct VSCRRegister {
  u8 sat = 0; 
  u8 nj = 0;  

  u32 Read() const noexcept { return static_cast<u32>(sat) | (static_cast<u32>(nj) << 16); }

  void Write(u32 word) noexcept {
    sat = static_cast<u8>(word & 1);
    nj = static_cast<u8>((word >> 16) & 1);
  }
};
 
}  // namespace rex::ppc
 
using PPCRegister = rex::ppc::Register;
using PPCXERRegister = rex::ppc::XERRegister;
using PPCCRRegister = rex::ppc::CRRegister;
using PPCVRegister = rex::ppc::VRegister;
using PPCFPSCRRegister = rex::ppc::FPSCRRegister;
using PPCVSCRRegister = rex::ppc::VSCRRegister;

struct alignas(0x40) PPCContext {
  PPCRegister r3;
  PPCRegister r0;
  PPCRegister r1;
  PPCRegister r2;
  PPCRegister r4;
  PPCRegister r5;
  PPCRegister r6;
  PPCRegister r7;
  PPCRegister r8;
  PPCRegister r9;
  PPCRegister r10;
  PPCRegister r11;
  PPCRegister r12;
  PPCRegister r13;
  PPCRegister r14;
  PPCRegister r15;
  PPCRegister r16;
  PPCRegister r17;
  PPCRegister r18;
  PPCRegister r19;
  PPCRegister r20;
  PPCRegister r21;
  PPCRegister r22;
  PPCRegister r23;
  PPCRegister r24;
  PPCRegister r25;
  PPCRegister r26;
  PPCRegister r27;
  PPCRegister r28;
  PPCRegister r29;
  PPCRegister r30;
  PPCRegister r31;
 
  u64 lr;             
  PPCRegister ctr;    
  PPCXERRegister xer; 
  PPCRegister reserved;
  u32 msr = 0x200A000;
  PPCCRRegister cr0; 
  PPCCRRegister cr1; 
  PPCCRRegister cr2; 
  PPCCRRegister cr3; 
  PPCCRRegister cr4; 
  PPCCRRegister cr5; 
  PPCCRRegister cr6; 
  PPCCRRegister cr7; 
  PPCFPSCRRegister fpscr;
  PPCVSCRRegister vscr;

  u32 last_indirect_target = 0;

  rex::kernel::ThreadState* thread_state = nullptr;

  rex::ppc::detail::DetourFrame* detour_frame = nullptr;

  PPCRegister f0;
  PPCRegister f1;
  PPCRegister f2;
  PPCRegister f3;
  PPCRegister f4;
  PPCRegister f5;
  PPCRegister f6;
  PPCRegister f7;
  PPCRegister f8;
  PPCRegister f9;
  PPCRegister f10;
  PPCRegister f11;
  PPCRegister f12;
  PPCRegister f13;
  PPCRegister f14;
  PPCRegister f15;
  PPCRegister f16;
  PPCRegister f17;
  PPCRegister f18;
  PPCRegister f19;
  PPCRegister f20;
  PPCRegister f21;
  PPCRegister f22;
  PPCRegister f23;
  PPCRegister f24;
  PPCRegister f25;
  PPCRegister f26;
  PPCRegister f27;
  PPCRegister f28;
  PPCRegister f29;
  PPCRegister f30;
  PPCRegister f31;

  PPCVRegister v0;
  PPCVRegister v1;
  PPCVRegister v2;
  PPCVRegister v3;
  PPCVRegister v4;
  PPCVRegister v5;
  PPCVRegister v6;
  PPCVRegister v7;
  PPCVRegister v8;
  PPCVRegister v9;
  PPCVRegister v10;
  PPCVRegister v11;
  PPCVRegister v12;
  PPCVRegister v13;
  PPCVRegister v14;
  PPCVRegister v15;
  PPCVRegister v16;
  PPCVRegister v17;
  PPCVRegister v18;
  PPCVRegister v19;
  PPCVRegister v20;
  PPCVRegister v21;
  PPCVRegister v22;
  PPCVRegister v23;
  PPCVRegister v24;
  PPCVRegister v25;
  PPCVRegister v26;
  PPCVRegister v27;
  PPCVRegister v28;
  PPCVRegister v29;
  PPCVRegister v30;
  PPCVRegister v31;
  PPCVRegister v32;
  PPCVRegister v33;
  PPCVRegister v34;
  PPCVRegister v35;
  PPCVRegister v36;
  PPCVRegister v37;
  PPCVRegister v38;
  PPCVRegister v39;
  PPCVRegister v40;
  PPCVRegister v41;
  PPCVRegister v42;
  PPCVRegister v43;
  PPCVRegister v44;
  PPCVRegister v45;
  PPCVRegister v46;
  PPCVRegister v47;
  PPCVRegister v48;
  PPCVRegister v49;
  PPCVRegister v50;
  PPCVRegister v51;
  PPCVRegister v52;
  PPCVRegister v53;
  PPCVRegister v54;
  PPCVRegister v55;
  PPCVRegister v56;
  PPCVRegister v57;
  PPCVRegister v58;
  PPCVRegister v59;
  PPCVRegister v60;
  PPCVRegister v61;
  PPCVRegister v62;
  PPCVRegister v63;
  PPCVRegister v64;
  PPCVRegister v65;
  PPCVRegister v66;
  PPCVRegister v67;
  PPCVRegister v68;
  PPCVRegister v69;
  PPCVRegister v70;
  PPCVRegister v71;
  PPCVRegister v72;
  PPCVRegister v73;
  PPCVRegister v74;
  PPCVRegister v75;
  PPCVRegister v76;
  PPCVRegister v77;
  PPCVRegister v78;
  PPCVRegister v79;
  PPCVRegister v80;
  PPCVRegister v81;
  PPCVRegister v82;
  PPCVRegister v83;
  PPCVRegister v84;
  PPCVRegister v85;
  PPCVRegister v86;
  PPCVRegister v87;
  PPCVRegister v88;
  PPCVRegister v89;
  PPCVRegister v90;
  PPCVRegister v91;
  PPCVRegister v92;
  PPCVRegister v93;
  PPCVRegister v94;
  PPCVRegister v95;
  PPCVRegister v96;
  PPCVRegister v97;
  PPCVRegister v98;
  PPCVRegister v99;
  PPCVRegister v100;
  PPCVRegister v101;
  PPCVRegister v102;
  PPCVRegister v103;
  PPCVRegister v104;
  PPCVRegister v105;
  PPCVRegister v106;
  PPCVRegister v107;
  PPCVRegister v108;
  PPCVRegister v109;
  PPCVRegister v110;
  PPCVRegister v111;
  PPCVRegister v112;
  PPCVRegister v113;
  PPCVRegister v114;
  PPCVRegister v115;
  PPCVRegister v116;
  PPCVRegister v117;
  PPCVRegister v118;
  PPCVRegister v119;
  PPCVRegister v120;
  PPCVRegister v121;
  PPCVRegister v122;
  PPCVRegister v123;
  PPCVRegister v124;
  PPCVRegister v125;
  PPCVRegister v126;
  PPCVRegister v127;

  const std::atomic<bool>* stop_requested = nullptr;

  rex::u32 GetCR() const noexcept {
    return (cr0.GetRaw() << 28) | (cr1.GetRaw() << 24) | (cr2.GetRaw() << 20) |
           (cr3.GetRaw() << 16) | (cr4.GetRaw() << 12) | (cr5.GetRaw() << 8) | (cr6.GetRaw() << 4) |
           cr7.GetRaw();
  }

  void SetCR(rex::u32 value) noexcept {
    cr0.SetRaw(value >> 28);
    cr1.SetRaw(value >> 24);
    cr2.SetRaw(value >> 20);
    cr3.SetRaw(value >> 16);
    cr4.SetRaw(value >> 12);
    cr5.SetRaw(value >> 8);
    cr6.SetRaw(value >> 4);
    cr7.SetRaw(value);
  }

  static constexpr size_t kNonVolatileCRCount = 4;

  static constexpr size_t kNonVolatileSaveSize =
      18 * sizeof(PPCRegister) + 18 * sizeof(PPCRegister) + 18 * sizeof(PPCVRegister) +
      64 * sizeof(PPCVRegister) + kNonVolatileCRCount * sizeof(PPCCRRegister) +
      sizeof(PPCFPSCRRegister);

  void SaveNonVolatiles(u8* dst) const {
    std::memcpy(dst, &r14, 18 * sizeof(PPCRegister));
    dst += 18 * sizeof(PPCRegister);
    std::memcpy(dst, &f14, 18 * sizeof(PPCRegister));
    dst += 18 * sizeof(PPCRegister);
    std::memcpy(dst, &v14, 18 * sizeof(PPCVRegister));
    dst += 18 * sizeof(PPCVRegister);
    std::memcpy(dst, &v64, 64 * sizeof(PPCVRegister));
    dst += 64 * sizeof(PPCVRegister);
    std::memcpy(dst, &cr2, kNonVolatileCRCount * sizeof(PPCCRRegister));
    dst += kNonVolatileCRCount * sizeof(PPCCRRegister);
    std::memcpy(dst, &fpscr, sizeof(PPCFPSCRRegister));
  }

  void RestoreNonVolatiles(const u8* src) {
    std::memcpy(&r14, src, 18 * sizeof(PPCRegister));
    src += 18 * sizeof(PPCRegister);
    std::memcpy(&f14, src, 18 * sizeof(PPCRegister));
    src += 18 * sizeof(PPCRegister);
    std::memcpy(&v14, src, 18 * sizeof(PPCVRegister));
    src += 18 * sizeof(PPCVRegister);
    std::memcpy(&v64, src, 64 * sizeof(PPCVRegister));
    src += 64 * sizeof(PPCVRegister);
    std::memcpy(&cr2, src, kNonVolatileCRCount * sizeof(PPCCRRegister));
    src += kNonVolatileCRCount * sizeof(PPCCRRegister);
    PPCFPSCRRegister saved_fpscr;
    std::memcpy(&saved_fpscr, src, sizeof(PPCFPSCRRegister));
    fpscr.RestoreGuestBits(saved_fpscr.csr);
  }
};
static_assert(offsetof(PPCContext, cr5) - offsetof(PPCContext, cr2) ==
                  (PPCContext::kNonVolatileCRCount - 1) * sizeof(PPCCRRegister),
              "cr2 to cr5 must be contiguous for the non volatile save area");
 
namespace rex::ppc {

struct BoundThread {
  PPCContext* ctx; 
  u8* base;        
};

REX_PPC_API BoundThread GetBoundThread();
 
namespace detail {

#ifndef NDEBUG
REX_PPC_API void CheckHookContext(const PPCContext& ctx, const char* name);
#else
inline void CheckHookContext(const PPCContext&, const char*) {}
#endif
 
}  // namespace detail
 
}  // namespace rex::ppc